|System-Level Design Roundtable from DAC 2013 Ed Sperling, part III|
The Future Of Verification. How verification is changing; validation vs. verification; the limits of divide and conquer; the impact of stacked die; questions about whether the lines are blurring between board and die; permanent employment for verification experts.
Nov 11, 2013
|System-Level Design Roundtable from DAC 2013 Ed Sperling, part II|
The Future Of Verification. New challenges as software and hardware need to be understood together; what defines success in verification tools and methodologies; shrinking the feedback loop between the designer and the verification process; can hardware verification ever catch up with growing complexity.
Nov 04, 2013
|Start Verification Early To Avoid Pitfalls Later|
It is well understood – at least from a theoretical point of view – that design verification should start as early as possible. The reality is that that doesn’t always happen for a variety of reasons such as enormous time to market pressure, too many new features to add, lack of foresight and discipline among other things. But progress is being made.
Oct 24, 2013
|Experts At The Table: Debug – Part II|
What are the big issues with debug? Semiconductor Engineering sat down with Galen Blake, senior verification engineer at Altera; Warren Stapleton, senior fellow at Advanced Micro Devices; Stephen Bailey, director of solutions marketing at Mentor Graphics; Michael Sanie, senior director of verification marketing at Synopsys. What follows are excerpts of that conversation.
Oct 24, 2013
|System-Level Design Roundtable from DAC 2013 Ed Sperling, part I|
The Future Of Verification. Raising the abstraction level and the effect on verification time; productivity measurements; the need to start verification earlier; concurrent issues; talk about a productivity gap resurfaces.
Oct 24, 2013
|Experts At The Table: Debug – Part I|
First of three parts: Multi-contextual debugging; IP Integration issues and who to call when you got a problem; why it’s taking more time to debug; limitations of tools; attitudes of IP development teams to customer issues.
Sep 26, 2013
|Debugging Verification Constraints|
Designs now can have 50-100K lines of constraints which leads to performance issues. The constraint solver under the hood of Synopsys's verification environment has been improved and that has sped things up, sometimes by as much as 25 times but more often just a factor of 2.
Jul 23, 2013
|Facing the Verification Management Challenge|
The integration of multicore CPUs, graphics coprocessors, modems, multimedia and networking facilities in the SoCs that power today’s sophisticated smartphones, tablets, computing and networking devices is creating a new verification challenge.
May 23, 2013
|Debugging the Debug Challenge|
Around 70% of the effort involved in taping out a complex SoC is spent on verification. Of that effort, about half, or 35% of the total effort involved in a chip design, is spent on debug.
Apr 04, 2013
|In Compliance We Trust, for Integration We Verify|
So, you dropped that piece of complex IP you just licensed into a SoC design, and now it is time to fire up the simulator. How do you verify that it actually works in your design? If you didn’t get verification IP (VIP) with the functional IP, it might be a really long day.
Mar 26, 2013
|Using VIP for Cache Coherency Hardware Implementations|
For multi-core SoCs, engineers have typically implemented cache coherency protocols in software. The shift to higher-performance, lower-power designs has led to an increasing preference for hardware implementations.
Feb 05, 2013
|Verification IP: The Questions You Should Ask|
Drop-in verification IP is a mythical creature: Unlike design IP, VIP users don’t have the luxury of ‘drag and drop’ implementations that require relatively little protocol expertise on the user’s part. Verification engineers need protocol knowledge to check that coverage is complete, properly interpret results and debug unexpected behavior.
Jan 24, 2013
|Verdi: No Requiem for Openness|
Verdi is probably the industry's most widely used debug system, widely used in verification groups. Historically it has been a very open system, not restricted to any one verification environment.
Jan 22, 2013
|The Industry Needs to Invest More in Debug|
For the past few years, nearly all surveys have identified design debug as one the toughest challenges faced by system-on-chip (SoC) developers. According to data collected by Synopsys from leading SoC, processor, graphics and networking designs, 35 percent of the engineering time and effort for a project typically is spent on debug.
Sep 18, 2012
|Managing coverage grading in complex multicore microprocessor environments|
In order to deliver ever increasing performance at bounded clock frequencies, processor vendors have turned to multicore designs that allow many programs to execute in parallel on a single chip. Verification of a multicore design is substantially more complex than a single core design because access to shared resources, such as the memory and I/O subsystems, requires arbitration and coherency. Not only general purpose processors, but embedded and application-specific processors such as graphics processing units (GPU), must be verified using large regression suites.
Jan 19, 2011
|Solving Modern Verification Challenges for Today’s Industry Leaders|
Chip complexity is driving verification requirements. As process nodes continue to shrink and complexity grows, the dominant problem faced by engineering teams lies not in actually creating new designs, but in creating them correctly, on time, while managing risk.
Nov 05, 2010
|The New Economics of Verification|
A more intelligent approach to verification can help design teams control the rising cost of chip design, according to Manoj Gandhi, senior vice president and general manager of Synopsys’ Verification Group.
Sep 13, 2010
|Generating AMD microcode stimuli using VCS constraint solver|
In this article, we explore using a hierarchical constrained-random approach to accelerate generation and reduce memory consumption, while providing optimal distribution and biasing to hit corner cases using the Synopsys VCS constraint solver. We present and analyze the method and discuss its effectiveness in today’s verification environment.
Jul 14, 2010
|Attacking Constraint Complexity: E Soft and SystemVerilog Default Constraints|
This two-part article series looks at a scalable constraint methodology and provides an overview of some of the key constraint optimization challenges and strategies of concern to verification engineers. Part 2 of this article series focuses on explores the similarities and differences, including subtle semantic differences, between E Soft Constraints and OpenVera Default constraints in the interest of optimizing constraint performance and speeding validation.
Mar 09, 2010
|Attacking Constraint Complexity: Verification IP Reuse|
This two-part article series looks at a scalable constraint methodology and provides an overview of some of the key constraint optimization challenges and strategies of concern to verification engineers. Part 1 of this article series focuses on verification IP reuse—detailing how a solver typically interprets constraints and providing a case study focused on a constraint-driven performance optimization strategy with respect to the flexible packet parser of a hypothetical networking ASIC.
Mar 02, 2010
|Formal verification with constraints: It doesn't have to be like tightrope walking|
The relentless increase in the number of transistors integrated on a single chip continues to take its toll on verification teams. Market pressures squeeze product development times, leaving little room for error.
Feb 02, 2010
|VCS Enables Efficient Constraint Solving and Debugging of SoC Design|
Yassine Even Amine, Applications Consultant at Synopsys, explains the considerations for a functional verification approach to debugging complex SoCs.
Oct 13, 2009
|Combining Formal Verification With Simulation: You Can Have Your Cake and Eat it Too! |
With ever-increasing design complexity and the desire to verify a design as exhaustively as possible, chip designers are increasingly interested in adopting formal verification methodologies.
Sep 08, 2009
|SystemVerilog and VMM Overcome WiMAX Verification Challenges|
SystemVerilog and VMM-based environment help achieve first pass silicon success by performing smarter verification quicker.
Aug 05, 2009