At the end of the project, Lee’s team found that by using the Synopsys FPGA flow, they were able to realize considerable savings in time and effort. "Overall, we saved about eight weeks of engineering time.""Mr. Eric Lee, Vice President of IC Technology, Silicon Data, Inc."
Silicon Data Background
Silicon Data, Inc. is a provider of highly integrated ASIC solutions that power broadband communications and networking. Using advanced chip design technologies and software techniques, Silicon Data designs, develops and provides complete turnkey solutions for home and small business networking, VoIP, wireless communications, and residential broadband gateways markets via OEMs. In this highly competitive market, cost and time to market are paramount. Therefore, the Silicon Data design team is always looking for ways to shorten the design cycle, while maintaining quality. To accomplish this, they use a suite of Synopsys tools, as well as variety of design and prototyping techniques.
The Design Challenge
One of Silicon Data’s latest designs was a two million gate ASIC, with twenty-one SRAM blocks and five main clocks running at 200 MHz, 100 MHz, 48 MHz and 33 MHz. For ASIC prototyping, the Silicon Data team used two Xilinx VirtexE 3200 FPGAs in an emulation system at around 2 MHz initially and up to 20-30 MHz, using their own board. The project was extremely schedule-driven and cost sensitive.
"We’re a startup without money to waste on new mask charges, so it’s extremely important to avoid doing a respin of a design," says Mr. Lee. "Our most critical design issue was getting the prototype up as quickly as possible without having to deviate from the ASIC flow or spending too much precious engineering resources getting the FPGA flow working. It’s ideal to use the same RTL database for both the FPGA and ASIC design. By using Synopsys tools, we could maintain the ASIC flow for both the FPGA and the ASIC.""We definately plan to continue using the FPGA prototyping
methodology for all future projects."
Meeting Customer Requirements
"The consumer market is very cost sensitive with short time-to-market market windows," Lee explains. "Being able to validate the whole system before taping out is a big advantage both in terms of NRE charges and in terms of engineering resources. By having a prototype ahead of time, we are able to give the software engineers a platform to develop the software in advance, as well as better validate our system. We depend on prototyping with FPGAs to achieve this concurrent engineering flow."
Synopsys Flow Produces Reliable Results the First Time
The EDA flow that Silicon Data relied on included Synopsys’ flagship synthesis product, Design Compiler, the Formality formal verification tool, HDL Compiler (Verilog), FPGA Compiler II, the VCS simulator, TetraMAX ATPG, the VERA Developers Kit, DesignWare intellectual property (IP), Design Vision and VERA Runtime.
"We decided on Synopsys when we learned that FPGA Compiler II used the same HDL compiler as Design Compiler," says Lee "FCII also has many sophisticated algorithms ensuring it doesn’t generate bad logic during synthesis. Competitive products tout runtime, but indications show that these products can synthesize bad logic, leading to more time in the lab debugging the FPGA. We knew that FPGA Compiler II was more likely to produce reliable results."
The Silicon Data team decided to go with Synopsys’ suggestion to instantiate their RAM primitives for synthesis. Instantiating was the best choice for this design for three reasons: memory allocation is optimized by hand which saves chip area; instantiating memories makes the technology transfer to or from an ASIC easier; and finally, there is less typing when entering HDL (VHDL or Verilog) when instantiating compared to memory inference. The Silicon Data team found this alternative very practical and discovered an additional advantage since they didn't need to write the simulation model for the SRAM module.
Silicon Data’s 2M gates SOHO gateway with Wireless Access Point
Silicon Data Realizes Success with FPGA Compiler II
At the end of the project, Lee’s team found that by using the Synopsys FPGA flow, they were able to realize considerable savings in time and effort. "Overall, we saved about eight weeks of engineering time," Lee concludes. "We caught a major bug we wouldn’t have caught in simulation. By not having to respin the chip at the fab, we saved considerable NRE charges (upwards of $250k or more). We’ve been able to develop software ahead of time and thus provide a more robust system in a shorter amount of time, which let us demo the system to our customers earlier. When we are able to bring our product to market ahead of schedule, our customers are able to ship their product to their customers earlier - an obvious advantage to all parties. Throughout the project, Synopsys support was excellent. We definitely plan to continue using the FPGA prototyping methodology for all future projects."