|Identifying and Resolving Low Power Issues Before Tapeout|
This webinar highlights how to find low power issues during verification using Formality.
Bob Hatt, Staff Corporate Applications Engineer, Synopsys
Sep 29, 2015
|Identifying and Resolving Low Power Issues Before Tapeout - Traditional Chinese|
This webinar highlights how to find low power issues during verification using Formality. - Traditional Chinese
Richard Su, Staff AC, Synopsys
Sep 29, 2015
|STMicroelectronics: Successful Last-minute Functional ECO Implementation with Formality Ultra|
STMicroelectronics describes how they used Formality® Ultra to meet their tight release schedule for their ARM® core based designs despite having to implement multiple functional ECOs late.
Kailash Digari, Group Manager CPU-GPU design, STMicroelectronics; John Lehman, Senior CAE Manager, Synopsys
Feb 05, 2015
|Verilog-to-Verilog Equivalence Checking Using ESP|
This Webinar gives a quick introduction to ESP-CV and how recent features are used to verify various Verilog-to-Verilog scenarios. Coverage analysis of the results is also discussed.
Philip Schmidt, R&D Manager, Synopsys; Dave Hedges, Corporate Applications Engineer, Synopsys
May 29, 2013
|Using ESP-CV for Faster Redundancy Verification in Memory Designs|
Learn how ESP-CV performs functional equivalence checks between a Verilog design and its transistor level implementation.
Dave Hedges, CAE, Implementation Group, Synopsys; Clay McDonald , R&D Manager, Implementation Group, Synopsys
Jan 19, 2011