LSI's Experience: New Formality Ultra Speeds Functional ECOs
Learn how Formality Ultra uses innovative matching and verification technologies to help designers cut in half the time they spend implementing manual ECOs late in the design cycle. Cason Kolb, Principal Design Engineer at LSI will describe their methodology for implementing and verifying functional ECOs during the different stages of the design cycle, the issues they face, and how Formality Ultra has helped speed their ECO implementation cycles.
Cason Kolb, Principal Design Engineer, LSI; Mitchell Mlinar, R&D Group Director of Formal Verification, Synopsys; and Mark Patton, Sr. Product Marketing Manager for Formality, Synopsys
Aug 08, 2013
Verilog-to-Verilog Equivalence Checking Using ESP
This Webinar gives a quick introduction to ESP-CV and how recent features are used to verify various Verilog-to-Verilog scenarios. Coverage analysis of the results is also discussed.
Philip Schmidt, R&D Manager, Synopsys; Dave Hedges, Corporate Applications Engineer, Synopsys
May 29, 2013
New Features and Methodologies for Simplifying Hierarchical Low Power Verification with Formality
This webinar will discuss new features in Formality to help make low power hierarchical verification easer. We will also cover how to write your power intent (UPF) to help you implement a robust, simplified, hierarchical verification flow.
Bob Hatt, Corporate Applications Engineer, Synopsys
Oct 10, 2012
Achieving Verification Success with Formality while Enabling the Best QoR with Design Compiler
Learn how Formality utilizes powerful links with Design Compiler that enable you to achieve maximum Quality of Results (QoR) while maintaining verifiability.
Joe Bosia, Corporate Applications Engineer, Synopsys
May 03, 2012
Meet Your Schedule with New ECO Verification and Other Enhancements in Formality
Hear about the new ECO Verification capabilities in Formality and other key new features, including its low power library checker, ease of use improvements and runtime enhancements.
Mark Patton, Product Marketing Director, Synopsys; David Low, Corporate Applications Engineer, Synopsys
Oct 27, 2011
Using ESP-CV for Faster Redundancy Verification in Memory Designs
Learn how ESP-CV performs functional equivalence checks between a Verilog design and its transistor level implementation.
Dave Hedges, CAE, Implementation Group, Synopsys; Clay McDonald , R&D Manager, Implementation Group, Synopsys
Jan 19, 2011
New Enhancements for Debugging Inconclusive and Non-Equivalent Verifications in Formality
This webinar will address what to do when faced with an inconclusive for non-equivalent design in Formality. Common types of failures will be discussed as well as suggestions for resolving them. New features in Formality 2010.03 will be presented which help the designer quickly identify the sources of the issue and makes recommendations on how to resolve them. Recent Formality low power enhancements will also be discussed.
Mitch Milner, R&D Group Director of Formal Verification
Jun 24, 2010
Successful Equivalence Checking of Highly Optimized DC Ultra Designs
Join us for an in-depth technical webinar focused on how to achieve successful verification on high-performance designs compiled with DC Ultra.
Mitchell Mliner, Synopsys
Apr 21, 2009