Formal Equivalence Checking for Custom Designs 

ESP is a formal equivalence checking tool commonly used for full functional verification of custom designs such as embedded memories, custom macros, standard cells and I/O cell libraries. It is used to ensure that two design representations are functionally equivalent. These designs may be described as behavioral Verilog Models, RTL, UDP’s, gates, or SPICE netlist views.

With the increasing complexity and importance of memories in modern ICs, there is a clear need for new tools and techniques for the design and verification of embedded memory blocks. ESP-CV puts formal technology into the memory designer's hands raising their confidence in the quality of the design, simplifying the testing process and increasing the overall verification productivity.
Key Benefits
  • Fast and broad coverage quickly finds bugs yielding higher quality
  • Supports new device technologies through Device Model Simulation and increases productivity
  • Directly verifies the SPICE netlist, eliminating the need for gate-level abstraction

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Library Verification
Library Verification provides a powerful environment that brings library cell verification capabilities into ESP Shell for a large group of simple matched designs.

Power Integrity Verification
ESP Power Integrity Verification detects common low-power and power-down errors and generates SPICE vectors for analysis and debug.

Redundancy Verification
ESP Redundancy Verification technology enables quick verification of redundancy logic used in embedded RAM designs that was implemented to bypass failing cells.

Interactive Signal Tracing
Interactive Signal Tracing provides a powerful environment for transistor-level debug. It allows users to query the cause of any transition, back-trace causal paths, and identify the source of X-values.

Power-up Re-initialization
The Power-up Re-initialization feature allows for the re-initialization of certain nodes within the powered-down portion of a design when power is reapplied.

Workshop: ESP-CV Basic and Advanced Training

  • Tuesday – Wednesday, March 1 - 2, 9:00 a.m. - 5:00 p.m.
  • Tuesday – Wednesday, June 14 - 15, 9:00 a.m. - 5:00 p.m.
  • Tuesday – Wednesday, September 27 - 28, 9:00 a.m. - 5:00 p.m.
  • Tuesday – Wednesday, November 29 - 30, 9:00 a.m. - 5:00 p.m.

Synopsys, 690 East Middlefield Road, Building A, Mountain View, CA 94043
To register for this class, contact your Synopsys support person.

Tuesday Memory 101
ESP-CV Basic Training using GUI:
  • Overview
  • ESP-CV Flow
  • Lab1
  • Debugging With ESP-CV
  • Lab2
ESP-CV Advanced Training: Symbolic Testbenches (using esp_shell):
  • Overview of Equivalence Checking
  • Symbolic Testbench Basic Components
  • Constraints for Equivalence Checking
  • Limitation of Symbolic Capacity
  • Lab 1
  • Symbolic coverage
  • Lab 2
  • Examples of Application Specific Symbolic Testbenches
  • Lab 3
ESP-CV Advanced Training: CKT modeling (using esp_shell):
  • ESP overview
  • Overview of RC switch level modeling
  • How to improve accuracy
  • How to debug RC switch modeling errors
  • Lab4
  • How to handle analog circuits
  • Lab5

By special arrangement, there is no charge for this class and space is limited.
Lunch will be provided.

Verilog-to-Verilog Equivalence Checking Using ESP
This Webinar gives a quick introduction to ESP-CV and how recent features are used to verify various Verilog-to-Verilog scenarios. Coverage analysis of the results is also discussed

Using ESP-CV for Faster Redundancy Verification in Memory
Learn how ESP-CV performs functional equivalence checks between a Verilog design and its transistor level implementation.