Synopsys at DVCon 2012 

Synopsys Activities at DVCon 2012 

TUTORIAL: UVM: Ready, Set, Deploy

Monday, February 27
8:30am – 5:00pm
Fir Ballroom

Dennis Brophy - Accellera Systems Initiative
Stanley Krolikoski - Accellera Systems Initiative
Yatin Trivedi - Accellera Systems Initiative

Universal Verification Methodology (UVM) as a standard and an open-source library has been available for more than a year. It continues to gain adoption across the verification community.

This tutorial will be presented by expert verification methodology architects and engineers. It will begin with an introduction to UVM, concepts of structured verification methodology, base classes, resource configuration management, error handling and report generation. The tutorial will continue with the UVM register package, including how to create and manage stimulus and checking at the register level.

The morning session will conclude with a review of all of the topics, showing how they fit together in a complex SOC verification environment.

Introduction of these fundamental concepts will be followed by several real-life user experiences including lessons learned in preparing transition to UVM, architecting reusable testbenches, debug techniques and use of TLM 2.0 in real verification environments.

This tutorial will appeal to new SystemVerilog users taking their first steps into constrained random verification as well as to power users looking to take advantage of the most recent developments in UVM. Working knowledge of SystemVerilog (IEEE 1800) and familiarity with at least one simulator is assumed.

Session 4T

Monday, February 27
3:30 – 5:00pm
Pine Ballroom

The North American SystemC Users Group (NASCUG) provides a unique forum for sharing SystemC user experiences among industry, research and universities. NASCUG operates independently but works in collaboration with the Accellera Systems Initiative to provide open forums for promoting information exchange. Our goal is to make SystemC end-users more effective through shared knowledge, user interaction and collaboration.

Find out more and register for NASCUG events at

BREAKFAST PANEL: Do we have what it takes for full-SoC verification?
Tuesday, February 28
7:30 – 8:30am

There is a growing consensus in the industry that full-chip verification of SoCs is at risk. The complexity of top-level testbenches and the slow speed of simulation has some questioning whether existing methodologies can cut it. Others argue that no testbench can verify a full SoC without links to test cases running on the SoC's embedded processors. Those who can afford simulation accelerators and emulators rely on running production code on the embedded processors. Still others argue that well-verified IP blocks mean that only connectivity checking is needed at the full-SoC level.

Moderator:Brian Bailey, Editor of EDA DesignLine
Panelists:Janick Bergeron, Synopsys

REGULAR SESSION: Low-Power Techniques

Tuesday, February 28
9:00 - 10:30am
Oak Ballroom

1.3 Is Power State Table (PST) Golden?

Speaker:Ankush Bagotra – Synopsys, Inc.
Authors:Ankush Bagotra – Synopsys, Inc.
Neha Bajaj – Synopsys, Inc.
Harsha Vardhan Dasagrandhi – Synopsys, Inc.

POSTER SESSION: Poster Session 1 - Coffee Break

Tuesday, February 28
10:30 – 11:00am
Gateway Foyer

1P.5 Chef's Special – An Efficient Verification Recipe for Maximizing Productivity While Using a Third

Speaker:Varun Sundaran – Synopsys, Inc.
Authors:Bhayik M. Vyas – Marseille Networks, Inc.
Abhisek Verma – Synopsys, Inc.
Arnit Sharma – Synopsys, Inc.
Varun Sundaran – Synopsys, Inc.

1P.7 Efficient Distribution of Video Frames to Achieve Better Throughput

Speaker:Kiran Maiya – Synopsys, Inc.
Authors:Kiran Maiya – Synopsys, Inc.
Surushi Jain – Marseille Networks, Inc.
Bhavik M. Vyas – Marseille Networks, Inc.

1P.10 An Integrated Framework for Power-Aware Verification

Speaker:Bhaskar Pal – Synopsys, Inc.
Authors:Harsh Chilwal – Synopsys, Inc.
Manish Jain – Synopsys, Inc.
Bhaskar Pal – Synopsys, Inc.

REGULAR SESSION: UVM Stimulus Generation
Wednesday, February 29
10:30am – 12:30pm
Oak Ballroom

10.2 ACE'ing the Verification of a Coherent System Using UVM

Speaker:Parag Goel – Synopsys, Inc.
Authors:Parag Goel – Synopsys, Inc.
Amit Sharma – Synopsys, Inc.
Romondy Luo – Synopsys, Inc.
Ray Varghese – Synopsys, Inc.
Acharya Satyapriya – Synopsys, Inc.
Peer Mohammed – Mindspeed Technologies, Inc.

10.4 Configuring Your Resources the UVM Way!

Speaker:Parag Goel – Synopsys, Inc.
Authors:Parag Goel – Synopsys, Inc.
Amit Sharma – Synopsys, Inc.
Rajiv Haija - Samsung

REGULAR SESSION: Verification Case Studies

February 29
10:30 – 12:30pm
Fir Ballroom

11.1 Exquisite Modeling of Verification IP: Challenges and Recommendations

Speaker:Adiel Khan – Synopsys, Inc.
Authors:Anuradha I. Tambad – LSI Corp.
Subashini Rajan – LSI Corp.
Imran Ali – LSI Corp.
Prashanth Srinivasa – LSI Corp.
Shivani Upsasani – LSI Corp.
Adiel Khan – Synopsys, Inc.

REGULAR SESSION: SystemVerilog Tips and Techniques

Wednesday, February 29
10:30 – 12:30pm
San Jose/Santa Clara Rooms

12.2 Soft Constraints in SystemVerilog: Semantics and Challenges

Speaker:Mark Strickland – Cisco Systems, Inc.
Authors:Mark Strickland – Cisco Systems, Inc.
HanLi Joseph Zhang – Cisco Systems, Inc.
Jason Chen – Synopsys, Inc.
Dhiraj Goswami – Synopsys, Inc.
Alexander Wakefield – Synopsys, Inc.

POSTER SESSION: Poster Session 2 - Coffee Break

Wednesday, February 29
10:00 – 10:30am
Gateway Foyer

2P.5 Registering the Standard: Migrating to the UVM_REG Code Base

Speaker:Adiel Khan – Synopsys, Inc.
Authors:Sachin Patel – Broadcom Corp.
Adiel Khan – Synopsys, Inc.
Amit Sharma – Synopsys, Inc.

2P.6 Tips for Developing Performance-Efficient Verification Environments

Speaker:Varun S – Synopsys, Inc.
Authors:Prashanth Srinivasa – LSI Corp.
Sarath Chandrababu Valapala – LSI Corp
Varun S – Synopsys, Inc.

2P.8 Leveraging ESL/TLM System Verification in RTL via UVM

Speaker:Ashok Mehta – Taiwan Semiconductor Manufacturing Co., Ltd.
Authors:Ashok Mehta – Taiwan Semiconductor Manufacturing Co., Ltd.
Albert Chiang – Synopsys, Inc.
Wei-Hua Han – Synopsys, Inc.

SPONSORED LUNCHEON: Industry Leaders Verify with Synopsys
Wednesday, February 29
12:30 – 1:45pm
Pine/Cedar Ballroom

Synopsys invites you to join us for lunch and a highly informative session covering the latest verification trends, challenges and solutions. You will hear leading industry experts discuss complex real-world verification challenges and present insights into best practices that help address them.

This luncheon provides a valuable opportunity to learn about new innovations in verification technology that enable improved performance and productivity. If you are a verification engineer or manager, you won't want to miss this special event.

KEYNOTE: Systemic Collaboration: Principles for Success in IC Design
Wednesday, February, 29
2:00 – 3:00PM
Oak/Fir Ballroom

Multi-dimensional systemic complexity is now moving across the IC design ecosystem. Simultaneously, trends indicate that the massive amount of software development needed across many domains is changing the way the players in the semiconductor industry understand their fundamental roles. Now, instead of making software to support new hardware, we are increasingly shifting to a perspective of making new hardware to support the software. The implications of this extend from analog to digital interactions and from system to silicon design and verification challenges. Engineers must struggle to differentiate their products in this rapidly evolving eco-system. In this presentation, Dr. de Geus will discuss several universal engineering principles that provide an architecture for how to think about the expanding roles of quality verification IP, models, and system-level solutions in the face of the economic and physical realities of advanced design.

Since co-founding Synopsys in 1986, Dr. Aart de Geus has led the growth of Synopsys from start-up synthesis enterprise to a diverse company that is a technology and market leader offering a complete integrated circuit (IC) design solution from concept to silicon. Aart has long been considered one of the world's leading experts on logic simulation and logic synthesis. Among the numerous industry honors Dr. de Geus has received was being named Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 1999. He was honored for pioneering the commercial logic synthesis market with the IEEE Circuits and Systems Society Industrial Pioneer Award in 2001 and in 2007 was awarded the IEEE Robert N. Noyce Medal for his "contributions to, and leadership in, the technology and business development of Electronic Design Automation."

Speaker: Aart de Geus - Synopsys, Inc.

TUTORIAL: New Levels of Verification IP Productivity for SOC Verification

Thursday, March 1
Donner Ballroom
Moderator: Neill Mullinger - Synopsys, Inc.

As the number of and complexity of IPs used on SOCs increases, there is a need for Verification IP (VIP) with improved methodology support, performance, productivity, ease-of-use, and debug. Reusability of tests and Verification IP is a major factor for productivity as verification progresses through multiple stages of detailed block verification, integration testing, and SOC verification. This tutorial will walk through the basic steps of installing, instantiating and using advanced verification IP in a UVM environment. It will show some of the more advance aspects of sequence generators, error injection and callbacks using extensive code examples. It will also show how to use many new features to help with planning, coverage, configuration and particularly debug that help to ramp on testbench development, quickly find issues and measure progress.

This session will conclude with a 30 minute demonstration to show new methods for protocol-based debug.

Registration Information:
You can add this tutorial to your Full Conference + 4 Tutorials, or Full Conference + 8 Tutorials package. If you would like to attend this tutorial only, the cost is $50.00. This includes coffee breaks, lunch and speaker slides on a USB Drive.

If you would like to register for this tutorial, CLICK HERE!

Speakers:Bernie DeLay - Synopsys, Inc.
John Elliott - Synopsys, Inc.