Synopsys at DVCon 2012 

Visit Synopsys at Booth #1105 

Tuesday, February 28, 3:30 - 6:30pm
Wednesday, February 29, 4:30 - 7:00pm

DoubleTree Hotel San Jose
Bayshore Ballroom
Map and Directions
DVCon 2012 Official Site
Synopsys Activities

Visit Synopsys at DVCon 2012 and learn more about the industry's most comprehensive System-to-Silicon Verification Solution

Today's expanding verification challenges require new, extended methodologies and solutions. Synopsys addresses these challenges by offering the industry's most comprehensive portfolio of system-level, hardware-assisted, functional, AMS, formal and low-power verification tools, models, IP, methodologies and services. The result is a single, comprehensive System-to-Silicon Verification solution that can help get your product to market sooner, more economically and with less risk.

Drop by our booth (#1105) to learn more about:

Verification IP: The latest advances in VIP productivity and methodology support.
Learn the latest developments with Synopsys Verification IP to improve the productivity of IP and SoC designers and verification teams
  • SystemVerilog
  • Support for UVM, VMM and OVM
  • High Performance
  • Productivity Tools
  • Debug Capabilities
  • Coverage Closure
  • Broad Portfolio of Titles
VCS: The Verification Solution of Choice for Industry Leaders
Learn how advancements in VCS help address the growing complexities of RTL verification.
Highlights of the demonstration include:
  • An overview of the industry's highest verification and performance capacity
  • Partition compile technology
  • Multicore auto-partitioning technology
  • Testbench and constrating debug
  • Support for UVM, VMM and OVM
  • MVSIM low power co-simulator
  • Hybrid formal verification with Magellan
  • Seamless integration with CustomSim circuit simulation and HAPS hardware prototyping solutions

FPGA-Based Prototyping: Accelerate System Validation of ASIC, ASSP and SoC Designs
See a demonstration on how Synopsys' FPGA-based prototyping solutions enable pre-silicon software development, hardware/software integration and system validation of complete systems at near real-time operating speeds using real-world interfaces. We will demonstrate the Universal Multi-Resource Bus (UMRBus) Interface for HAPS products which delivers programmability and flexibility without compromising "at-speed" system performance.

Be sure to join us for the sponsored lunch Industry Leaders Verify with Synopsys on Wednesday Feb. 29 from 12:30 to 1:45 in the Pine/Cedar Ballroom. This luncheon is immediately prior to Aart de Geus' keynote address titled Systemic Collaboration: Principles for Success in IC Design 2:00 – 3:00pm in the Oak/Fir Ballroom.

See all Synopsys activities at DVCon 2012

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