Today’s advanced process technologies and faster time-to-market schedules are pushing the limits of verification tools. Post-layout simulation runtimes are increasing 2-4x with every new process generation as chip transistor counts double and new parasitic effects come into play. The Synopsys StarRC™ extraction solution offers a wide range of features to boost the simulation performance and capacity of transistor-level custom digital, analog/mixed-signal and memory designs.
Omar Shah, Corporate Application Engineer; Shekhar Kapoor, Marketing Manager

Accurate parasitic extraction is critical to the success of high-performance integrated circuit (IC) design due to its impact on circuit timing, signal integrity and functionality. Synopsys’ StarRC™ Fast Field Solver (FFS) solution with Raphael NXT offers high-accuracy 3D capacitance extraction with full-chip performance and capacity for reference validation and signoff analysis. This paper presents the StarRC FFS solution and the benefits it provides to IP and IC designers.
Omar Shah, Corporate Application Engineer; Shekhar Kapoor, Marketing Manager

Consider the number of checks that an IC design team has to go through before tape-out. In each company, chip failures ultimately translate into additional checks in the sign-off flow. Technology and design trends are responsible for further increasing the number of checks.
Bradley Geden Product Marketing Manager, AMS Circuit Simulation, Synopsys, Inc.