DAC 2009: AMS Verification Videolog. 


Coping with Modern AMS Verification Challenges

On July 28, 2009, Synopsys hosted an AMS Verification Breakfast event at DAC in San Francisco, CA focused on using Synopsys’ CustomSim™ unified circuit simulation solution to overcome modern AMS verification challenges and deliver leading-edge technology products.

The guest panel of industry experts discussed how they are addressing key verification challenges at 32 nanometers, achieving high-accuracy verification for complex BCD and FPGA applications, and using power management techniques for custom DSP designs.

Speakers:

John Chilton, Emcee
Sr. VP of Marketing & Corporate Development, Synopsys


Aaron Barker
Staff Engineer, Microelectronics, Processor Design Tools,
Sun Microsystems

Nanometer Processes Verification Challenges


Eugene Chen
CAD Director, Altera
High-speed Circuit Simulator Requirements


Sandeep Tare
Verification Methodology Engineer, Wireless Business Unit,
Texas Instruments

Mixed-Signal Verification, Need, Scope & Challenges


Lyes Djama
Smart Power Design Flows Manager

Pierluigi Daglio
AMS Design & Verification Flows Manager
STMicroelectronics

Comprehensive AMS Verification Solutions



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