HSIMplus™ HDL Co-simulation enables simulation of designs that consist of a combination of SPICE transistor-level circuit netlists and Verilog gate or RTL-level digital modules. By combining the capacity and performance of HSIM with Verilog simulation in Synopsys VCS®, designers can perform comprehensive mixed-signal analysis to gain a full chip view of complex SoC designs.
Logic and circuit designs are often performed by different teams, using different database formats and languages. HSIMplus HDL Co-simulation connects digital and analog design flows to enhance simulation performance for large mixed-signal circuits. Co-simulation is often used early in a design, before the SPICE netlist is available, or to incorporate models of Silicon IP for which a circuit description is not available. By applying HDL Co-simulation, testbenches written in Verilog can be re-used for more accurate circuit-level simulation, without the need for test vector generation and conversion.
- HSIMplus HDL Co-simulation Features
- Built on the industry-standard PLI 2.0; providing an interface from HSIM to compliant Verilog simulators, including Synopsys VCS®, Cadence NC-Verilog, and Mentor ModelSim®
- Co-simulation executes as a single process
- Interface A2D and D2A elements inserted automatically
- Automatic voltage level detection automatically identifies voltage levels at interface nodes
- HSIM interactive mode with save-restart is available for debugging
- Supports user's choice of flows
- Verilog top level: SPICE subcircuit instances replace module instances
- HSIM top level: Verilog module instances replace SPICE subcircuits
- Integration with Virtuoso® Analog Design Environment with analog and digital netlists generated by SPECTRE/Verilog co-simulation.