In deep sub-micron designs, interconnect delays determine system performance. Extraction tools and high capacity simulators are often used at the end of design flow as the final verification step prior to tape-out. Because of the additional parasitic elements, the post-layout netlist connectivity is dramatically different from the ideal schematic. The process to correlate results from post-layout simulation to its original design is very time-consuming, if not impossible.
As an option of Sandwork SpiceExplorer debugging environment, the ChipView module fills the missing link for post-layout verification. The ChipView module first processes the embedded information in extracted netlist to build a pseudo-layout view. Designers can then utilize this pseudo-layout to quickly map extracted nets to original nets, or locate extracted nets/elements automatically generated from the extracted netlist. Additionally, ChipView also supports back annotation to the original ideal schematic via the SX-Link package.
- Visualize electrical impact of interconnect
- Supports DSPF netlist format
- Pseudo-layout view automatically generated from extracted netlist
- Zoom in/out, panning functions in the pseudo-layout view
- Back annotation from extracted nets to original schematics
- Direct netlist cross-probing from the pseudo-layout into WaveView Analyzer