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A View from the Top: A System-Level Blog
This blog will deal not only with the shift towards adoption of virtual platforms but with ESL technologies in general.
F. Schirrmeister, J. Stahl, M. Serughetti, T. Schutter, P. Sheridan
Analog Insights Blog: Analog/Mixed-Signal Design and Verification
Observations and views from 3 of Synopsys’ top AMS/custom design technologists.
Fred Sendig, Kishore Singhal, Bob Lefferts
Verification Martial Arts
In SystemVerilog, unlike C, you don’t have to explictly free dynamically allocated class instances.
Janick Bergeron
The Standards Game
Hello, everyone interested in EDA interoperability and fans of The Standards Game. I’d like to invite you to join me at the 21st Synopsys EDA Interoperability Forum, sponsored by Sun Microsystems.
Karen Bartleson
All Synopsys Blogs
DAC AMS LUNCH
Advance Your Mixed-signal Verification Techniques to the Next Level
DISCOVERY-AMS WEBINAR
Mixed-Signal Verification — An ST-Ericsson Case Study
HSPICE SIG VIDEOLOG
Leading-edge Modeling for Chip, Package and 3D-IC
DAC Custom Design Lunch
Addressing Custom Design Challenges with Laker
SILICONSMART WEBINAR
Eliminate the Digital Implementation Bottleneck with Fast and Accurate Library Characterization
News
Micronas Standardizes on Synopsys’ Design and Verification Solutions for....
Latest Advances in FineSim Deliver Up to 2X Performance and Capacity Improvements
Synopsys Accelerates Adoption of FinFET Technology with Production-Proven....
Synopsys to Acquire SpringSoft
Synopsys Acquires Ciranova
Synopsys Mixed-Signal IC Design Solution Qualified for TowerJazz Power....
Synopsys Completes Acquisition of Magma Design Automation
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All Synopsys News
Articles
How VHDL designers can exploit SystemVerilog
Synopsys tries to organize its efforts in EDA multiprocessing
Verify SoCs Faster And More Predictably With SystemVerilog And Constrained-Random Stimuli
VMM application packages- the next level of productivity
IC verification key: ‘Do it step by step, don’t cut corners’
Nightmares in Functional Verification
Future Verification Appears Uncertain
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Blogs
A View from the Top: A System-Level Blog
Analog Insights Blog: Analog/Mixed-Signal Design and Verification
Verification Martial Arts
The Standards Game
More
White Papers
Custom and Mixed-Signal Design Solution
Understand and Avoid Electromigration (EM) & IR-drop in Custom IP Blocks
MOS Device Aging Analysis with HSPICE and CustomSim
Using Digital Verification Techniques on Mixed-signal SoCs with CustomSim and VCS
Automated Regression for Mixed-Signal Verification
De-risking Variation-aware Custom IC Design with Solido Variation Designer and Synopsys HSPICE
IC Validator: Physical Verification for Analog Designs
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Webinars
Discovery-AMS for Mixed-Signal Verification
Open Your Eye with HSPICE
Fast and Accurate Library Characterization
High-Productivity Analog Verification and Debug
Get the Most from Your HSPICE Simulation
Avoid EM & IR-drop Effects in Custom IP Blocks
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Videos
DAC 2012: Boost Productivity Using Synopsys’ AMS Verification Solution
2012 HSPICE SIG Event: Tackling Design Integrity of Multi-Gbps Systems
DAC 2011: SPICE Up Your Chip: Achieving Fast, Accurate AMS Verification
CustomExplorer Ultra: Mixed-signal Regression Management and Debug Environment
HSPICE SIG: A Converging Analog World: Silicon, Package and System
DAC 2010: Coping with Modern AMS Verification Challenges
DAC 2009: Coping with Modern AMS Challenges
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HSPICE Essentials
NanoSim
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