Videos 

2013 HSPICE SIG Event: Leading-edge Modeling for Chip, Package and 3D-IC
2013 HSPICE SIG Event: Leading-edge Modeling for Chip, Package and 3D-IC

On January 29, 2013, Synopsys hosted an HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about their experiences using HSPICE in some of their most challenging designs.
Fuad Badrieh, Principal Engineer, Micron; David Banas, Sr. MTS, Micron; Gladney Asada, MTS, AMD; Scott Wedge, Sr. Staff Engineer, Synopsys


2012 HSPICE SIG Event: Tackling Design Integrity of Multi-Gbps Systems
2012 HSPICE SIG Event: Tackling Design Integrity of Multi-Gbps Systems

On January 31, 2012, Synopsys hosted an HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about their experiences using HSPICE in some of their most challenging designs.
Tony Todesco, SMTS Design Engineer, AMD; Johann Nittman, Signal Integrity Engineer, Cavium Networks; Liping Li, Sr. Member of the Technical Staff, Altera; Randy Wolff, Manager, Signal Integrity R&D Group, Micron; Scott Wedge, Sr. Staff Engineer, Synopsys



Introducing HSPICE Precision Parallel Technology

HSPICE Precision Parallel technology, coupled with enhanced convergence algorithms, advanced analog analysis features and foundry-qualified process design kits, extends HSPICE for verification of complex analog and mixed-signal designs. Its highly scalable algorithm delivers up to 7X speed-up on 8-core CPUs while maintaining golden HSPICE accuracy. HSPICE Precision Parallel technology enables design teams to accelerate verification of analog circuits from days to hours.
Frank Lee



DAC 2011: SPICE Up Your Chip: Achieving Fast, Accurate AMS Verification

On June 7, 2011, Synopsys hosted an dinner event at DAC in San Diego, CA. Hear what industry leaders from AMD, Juniper Networks, nVidia, Qualcomm and Xilinx had to say about using HSPICE and CustomSim in some of today’s most challenging designs.
Dirk Robinson, Analog Design Engineer, AMD; Nikhil Jayakumar, Design Engineer, Global Circuits Team, Juniper Networks; Wen-Hung Lo, Senior Mixed-Signal Design Engineer, NVIDIA; Mohamed Abu-Rahma, Staff Engineer, Memory Circuit Design Team, Qualcomm; Min-Fang Ho, CAD Manager, IC CAD, Xilinx


HSPICE SIG Video
HSPICE SIG: A Converging Analog World: Silicon, Package and System

On January 31, 2011, Synopsys hosted its first HSPICE SIG Event in Santa Clara, CA. At this event, industry leaders spoke about using HSPICE in some of today's most challenging designs.
Synopsys, Inc.


HSPICE Mini Demos

See how HPP technology and StatEye analysis can speed up simulation of analog circuits!
Synopsys, Inc


IMS MicroApp Video: Causality Considerations for Multi-Gigabit StatEye Analysis

Mike Heimlich, AWR Corp., Ted Mido and Scott Wedge, Synopsys present "Causality Considerations for Multi-Gigabit StatEye Analysis" as part of the IEEE.tv showcase of MicroApps seminars from the IEEE MTT International Microwave Symposium (IMS), held in Anaheim, California, May 23-28, 2010.
Synopsys, Inc. and AWR Corp.




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