Hierarchical Full-chip Circuit Simulation and Analysis  

The need for high-capacity, high-performance transistor-level verification has increased as nanometer silicon effects now dominate design performance. Today’s designs require precise control of leakage effects to meet power budgets, at the same time that reduced supply voltages and increased interconnect parasitics leave little design margin for meeting performance specifications. HSIM is uniquely architected to meet the challenges of circuit verification at 65nm, 45nm and below through its innovative hierarchical simulation engine - delivering the capacity you need for precise analysis of post-layout effects. Analog, mixed-signal, memory and SoC designs benefit from the ability to perform more extensive transistor-level analysis while overcoming the inefficiencies of flat SPICE simulators. HSIM increases confidence in results before tapeout, to deliver predictable success.

HSIM Features
  • Full SPICE functionality; including AC, DC, transient, Monte Carlo and FFT analyses
  • HSIM Input formats:
    • HSPICE including triple DES (3DES) and Verilog-A encryption
    • Spectre and Eldo-format netlists
    • VCD and HSPICE vector stimulus
    • Interpreted and compiled Verilog-A
    • DPF, SPEF, and DSPF parasitic formats
  • HSIM Output formats:
    • ASCII .out and raw formats
    • WSF, PSF, PSF-float
    • WDF
    • FSDB
    • UTF
    • .measure, built-in timing and power checks
  • Built-in parasitic reduction algorithms
  • Integration with Cadence Virtuoso Analog Design Environment

HSIM™ delivers superior performance and capacity over traditional SPICE-based simulators, by applying two innovative and proprietary techniques:

  • Hierarchical Storage and Isomorphic Matching

Hierarchical Storage
Traditional SPICE-based simulators employ matrix-solving algorithms that must flatten the hierarchy that designers build into their circuit, in order to simultaneously solve for all node voltages and branch currents at every time step in a simulation. The hierarchical solver in HSIM exploits design hierarchy; increasing performance and reducing memory storage requirements by partitioning the simulation database into a set of smaller matrices that can be solved independently.

HSIM Hierarchical Storage

Isomorphic Matching
HSIM further exploits circuit hierarchy by dynamically recognizing that the state of a circuit at any time step may include multiple instances of identical cells, with terminal voltages and currents that are also identical. Through proprietary isomorphic matching algorithms, HSIM increases simulation efficiency by eliminating redundant calculations, solving each cell just once for all isomorphically matched instances. This technique is especially beneficial to circuits that contain large memory blocks with many identical bit cells.

HSIM Isomorphic Matching

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