Webinars 

Galaxy Custom Designer--A Complete Custom Implementation Flow
Follow the front-to-back development of an AMS block using Synopsys' Galaxy Custom Designer implementation solution.
Joe Mastroianni, VP of R&D, Les Spruiell, Product Marketing Manager, and Chris Shaw, Technical Marketing Manager
Nov 03, 2009

Robust SI Analysis of a DDR2 Interface with HSPICE
For years designers around the world have trusted HSPICE for their signal integrity simulation needs. For video memory and many other applications, increases in chip and board speeds over the last few years have created significant and widespread demand for accurate signal integrity analysis. This tutorial walks through the setup, simulation and analysis of a Synopsys DDR2 memory interface highlighting HSPICE’s signal integrity analysis features.
Dr. Scott Wedge Senior Staff Engineer, Synopsys Ted Mido Senior Staff Engineer
Feb 13, 2007

Predicting PLL Phase Noise & Jitter with HSPICE RF
Due to today’s ever increasing data rates, phase noise and jitter specifications are now critical aspects of modern phase-locked loop design. Accurate predictions of PLL noise are possible through circuit simulation, but the steps required to do so are often shrouded in mystery or considered too challenging to undertake. This tutorial outlines a procedure for efficiently extracting key phase noise and jitter measurements for phase-locked loops using many of the unique simulation capabilities of HSPICE RF.
Dr. Scott Wedge Senior Staff Engineer, Synopsys
Jan 23, 2007

Nov.7 Archived Webcast HSIMplus – Beyond FAST Spice Simulation – Listen Now!
Fast-SPICE simulation in the past was limited primarily to functional verification, because the gains achieved in simulation performance required giving up on SPICE accuracy.
Mike Demler Cheryl Ajluni Giuseppe Oliva
Nov 07, 2006

Faster Verification Performance with VCS Native Testbench and RVM
The Native Testbench feature of Synopsys' VCS comprehensive RTL verification solution enables both design and advanced testbench to be compiled together for up to 5x faster verification performance.
Synopsys, Inc.
Mar 30, 2005

Static Verification with LEDA in Discovery Verification Platform
Come join us for a one-hour live webcast to see how Synopsys addresses these design verification problems with LEDA, a programmable mixed language RTL and gate design checker in the Discovery Verification platform.
Synopsys Inc.;
Aug 13, 2003

Introduction to SystemVerilog
With designs continuing to increase in size and complexity, today's design and verification methodologies are being stressed to the breaking point.
Synopsys inc.;
Oct 17, 2002

Introduction to Assertion-Based Verification
Ever increasing design size and complexity are stressing current verification methodologies.
Synopsys inc.;
Aug 13, 2002



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