The cross-sectional view of the simulated PDSOI pMOS (left) and nMOS (right) device. The physical gate length is 30 nm and the gate stack consists of 20A HfO2 on top of 5A Oxide.
Drain current as a function of drain voltage for the pMOS (left) and the nMOS (right) for a gate bias 20% above the respective threshold voltage (lower set of curves) and twice the respective threshold voltage (upper set of curves).
The solid lines show the results for the floating body devices, while the dashed curves give the results for devices for which floating body effect are suppressed by introducing an (artificial) body tie contact. It can be seen that at medium drain bias the charging-up of the floating body results is a slight increased drain current. At higher drain bias impact-ionization at the drain-side pn-junctions result is a sharp increase of the drain current ("Kink effect").
Overview
Partially depleted silicon-on-insulator (PDSOI) transistors are widely used for high-performance VLSI CMOS, because of significantly reduced junction capacitances and an increased speed compared with bulk silicon MOSFETs. However, PDSOI suffer from floating-body effects. Depending on the bias conditions and even the biasing history, generation and recombination processes can charge up the floating region. These charges act as an effective back-gate bias and change the current-voltage characteristics of the PDSOI quite significantly. Floating-body effects are determined by delicate balance between various generation and recombination mechanisms, and make numerical simulation of PDSOI devices a very challenging task. This Application Note showcases process and device simulations of partially depleted SOI CMOS devices with TCAD Sentaurus.
The Sentaurus Process simulations are performed using the three-stream diffusion model with charged point defects. Latest analytical implantation models are utilized in process simulation in order to generate ultra-shallow junction profiles and account for the point generation and damage accumulation. The parameters and models for the different process steps are set by Synopsys Advanced Calibration module. Hafnium oxide (HfO2) is used as a part of the dielectric stack. The simulated process flow also includes a combination of spike and laser anneal to activate the dopants and limit the diffusion at the same time. Process induced stresses such as stresses from trench fill material, stress memorization effects (SMT) in polysilicon (NMOS device only), SiGe pockets (PMOS device only) and dual stress liners (DSL) are also accounted for. The transistors also feature metal-last replacement gates.
The Sentaurus Device simulations include hydrodynamic carrier transport as well as quantum corrections based on the density gradient model. The mobility models include high-k dielectric enhancements to the Lombardi mobility model to simulate the mobility degradation at the HfO2 dielectric stack interface.
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