The process flow represents a generic 90 nm technology node and is intended to serve as a convenient starting point for any deep submicron CMOS simulation project. The setup of the Sentaurus Workbench (SWB) project supports NMOS and PMOS devices, and allows for the simulation of structures with different gate lengths. Other variations can be included by adjusting the template. The Sentaurus Workbench template project also performs certain device simulations to extract key electrical parameters in order to facilitate customized calibration and optimization projects.
Magnification of gate-drain area of 90 nm gate length NMOS device as simulated by Sentaurus Process; concentrations of dopants in various regions are shown.
Drain current as a function of gate voltage for the 90 nm gate length PMOS (red) and NMOS (blue) devices simulated with Sentaurus Device; lower curves (solid lines) are for a drain bias of 50 mV and upper curves (dashes) are for 1.2 V
The simulation project is part of the Sentaurus TCAD distribution at:
If you are interested in accessing this Application Example, please fill out the Example Request Form and you will be emailed download instructions.