This Sentaurus TCAD simulation project provides a template setup for farsubmicron CMOS device characterization. IdVgs curves for a low drain bias and high drain bias are simulated for NMOS and PMOS structures with various gate lengths. In addition, for selected structures, a family of IdVds curves for various gate biases is simulated and small-signal simulations are performed to obtain the CV characteristics of the respective devices. For each of the simulated curves, relevant electrical parameters, such as threshold voltages and drain current levels, are extracted. Finally, the extracted parameters are plotted as a function of the gate length.
Drain current as a function of drain voltage for the 90 nm gate length PMOS (left) and NMOS (right) devices simulated with Sentaurus Device; gate bias for curves is 0.6 V (blue), 0.9 V (green), and 1.2 V (red).
Total gate (Cgg, red), gate-contacts (Ccg, green), and gate-body (Cbg, blue) capacitance as a function of gate voltage for 90 nm gate length NMOS device simulated with Sentaurus Device.
Threshold voltage as function of gate length for NMOS (red) and PMOS (blue) devices.
The simulation project is part of the Sentaurus TCAD distribution at:
If you are interested in accessing this Application Example, please fill out the Example Request Form and you will be emailed download instructions.