Abstracts
In back end of line (BEoL) processing, high mechanical stresses and large stress gradients in local regions of interconnect structures can lead to yield loss and reliability failures ranging from dielectric cracking and metal voiding to interface debonding and layer delaminations. Stress related failures have become even more significant with the adoption of low-k dielectric materials, which have low mechanical strength and a large thermal expansion coefficient. More recently, intrinsically stressed dielectric layers have been applied as stress sources in leading edge CMOS technologies to engineer beneficial stress in MOSFET channels to enhance electron and hole mobilities.

Fammos TX is a Synopsys TCAD product which analyzes stress evolution in interconnect processes and in dual stress liners (DSL) used in strained-silicon CMOS technologies. This webcast shows how Fammos TX generates complex 3D structures from GDS II and process data and illustrates its applicability to process integration challenges in interconnect and strained-silicon structures.

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