Overview
3D integration, where multiple die are stacked and interconnected in the vertical dimension using through-silicon vias (TSVs), is considered by many to offer significant performance and cost benefits for key applications. In traditional ICs, stress modeling is used to help ensure the reliable operation of the interconnect materials. In 3D ICs, the stress-related challenges become more severe due to the presence of thin die, bonding layers, redistribution lines between the die and TSVs. Examples of TSV-induced stress include the degradation of transistor performance due to stress induced on transistors by adjacent TSVs and the breakage of interconnect lines connected to TSVs. These new sources of stress need to be accurately modeled to drive the creation of appropriate design rules for reliability and yield for 3D ICs.

Synopsys’ Fammos is a 3D finite element analysis tool designed to analyze these reliability issues. This webcast discusses the modeling approach used in Fammos and various applications to model 3D integration problems.

Who Should Attend?
Technology development engineers, reliability engineers, engineers/managers working on Back-end-of-line process design, product integration engineers, and packaging engineers

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