TCAD Application Power Devices Example  

Simulation of 4H-SiC Vertical Junction FET in Sentaurus Device 

Figure 1
Figure 1: Device structure, doping profile and simulation mesh of VJFET; inset shows mesh refinement surrounding the critical regions at the bottom of the vertical channel

Figure 2
Figure 2: Measured (points) and simulated (lines) IdsVds characteristics of VJFET. Gate voltages in parentheses are the actual gate voltages. The discrepancy is due to gate contact resistance, which is not explicitly considered in the simulation

Overview
Silicon carbide (SiC) has long been recognized as a superior semiconductor for high-power and high-temperature applications in view of its high breakdown electric field and excellent thermal conductivity. Since the pioneering work of Tairov and Tsvetkov who developed the modified seed sublimation growth process that spearheaded today's SiC substrate technology, the industry has improved steadily the quality, size, and cost of SiC substrates, all of which are key manufacturability considerations in any semiconductor technology.

TCAD simulations rely on physical models describing the operational phenomena and model parameters calibrated to the process and materials used to fabricate the devices. The key material and model parameters were compiled for the 4H-SiC polytype.

Both IdVds and breakdown simulations are presented for a 4H-SiC normally off¡Çvertical junction FET. The device structure is taken to be similar to the one discussed by Zhao et al. [1], and the simulation results are compared to the experimental results shown in the literature [1]. The simulation project contains a model parameter file that is calibrated specifically for 4H-SiC.

[1] J. H. Zhao et al., "3.6 mΩm2, 1726 V 4H-SiC normally-off trenched-and-implanted vertical JFETs and circuit applications," IEE Proceedings Circuits, Devices and Systems, vol. 151, no. 3, pp. 231237, 2004.

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