Doping distribution in twin silicon nanowire NMOS FET transistor. The trench, gate and spacer regions are shown transparent. A quarter of the device is shown.
Plot of the mesh for device simulation. Detailed view of the mesh in the channel is presented in the upper left corner.
Modern semiconductor industry is facing numerous challenges as the next generation of devices are developed and manufactured. The complexity of the newly developed devices requires that more and more aspects of their operation be well understood. In order to keep up with Moore’s law requirements, device dimensions of conventional CMOS technologies are being constantly shrunk. At the same time, entirely new types of devices such as FinFETs, tri-gate transistors or inverted-T FETS, are seen as the next step in semiconductor technology development. The common feature of these new device types is that they are inherently three-dimensional in nature and cannot be adequately represented in two-dimensional simulation. A reliable three-dimensional simulation tool is becoming a necessary part of the development cycle in order to gain better understanding of the processes, shorten the development cycle and decrease the costs.
Three-dimensional simulations present numerous challenges to software developers; with the main ones being meshing, moving boundary simulation and numerical challenges. This month’s featured application example demonstrates the three-dimensional capabilities of Synopsys TCAD for future generation devices; both full process and device 3D simulations for Twin Silicon Nanowire FinFET (TSNWFET) device are presented.
Three-dimensional process simulation is performed using Sentaurus Process with integrated Sentaurus Structure Editor library. In this new approach the simulation is driven by a single tool, Sentaurus Process, and 3D geometric operations are performed via runtime calls to the Sentaurus Structure Editor library. The electrical characteristics of the device were simulated in 3D with Sentaurus Device.
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