Variation in electrical parameters like mobility, drive current, leakage current and threshold voltage is a major challenge to circuit design, yield and performance in advanced technologies. This variation can be caused by different physical effects like lithographic proximity effect in sub-wavelength technologies, well proximity effects and various stress sources (intentional and unintentional) in the design. These effects extend beyond a single isolated device and it becomes necessary to capture the layout context dependencies of the electrical variation at the transistor level. The tools Seismos CX and Seismos LX map layout dependent physical variation to electrical variation at the transistor instance level for a better circuit design.