Highlights

• Embedded Processor Models
• Interconnect Models
• Peripheral Models
• Memory Subsystem Models
• Custom Processor Models

Synopsys Models for Platform Architect are a collection of SystemC transaction-level models, including embedded processors, interconnects, peripherals, and memories. These models are representive of the IP needed by designers to be able to build platforms, verify interconnect architectures, debug hardware and software and verify the design before moving to the RTL implementation flow.

Models for Platform Architect have been developed in partnership with major IP providers, including the market leaders ARM, IBM, MIPS, Toshiba, Tensilica, Sonics, CEVA and VeriSilicon, giving the designer access to IP vendor reference models and ensuring correct behavior. Other semiconductor IP partners provide models directly to the customer.

Embedded Processor Models
Embedded Processor Models use Instruction Set Simulators (ISS) to simulate the behavior of the implementation model. By being an abstract representation of the RTL, the simulation performance gained is typically several orders of magnitude faster than the implementation model. This allows hardware and software designers to run more application code or more comprehensive verification suites to prove the design.

Synopsys works with the designer's IP partners on ISS model certification by the partner, ensuring that the models have the correct functionality and behavior available for SystemC simulation. Based on many years of experience, Synopsys also works with many IP Partners to enable them to most efficiently create their own SystemC-compatible processor models that support features such as virtual memory, debugging and analysis to maximize the value of these models within Platform Architect and Model Designer.

With Processor Designer Synopsys offers a unique tool that enables customers to create dedicated and highly optimized processors (see Custom Processor Models) and eases and optimizes the creation of fast instruction accurate processor models. Synopsys Processor Designer automatically creates the Instruction Set Simulator (at both instruction accurate and cycle-accurate levels), from the LISA description language. All necessary software tools are generated, including assembler, disassembler, linker, profiler and debugger. Combined with Synopsys’ ESL transaction-level methodologies and Synopsys virtual prototypes, these fast processor models enable early software development.

Interconnect Models
Whether platforms are created from scratch, or by mixing legacy blocks with newly-created functionality, it is critical that designs are easily created and validated. Synopsys’ Bus Library Wizard (BL Wizard) uses Transactional Bus Simulators to automatically generate the designer's specified interconnect architecture for the platform. The resulting platform can be simulated at the transaction-level for maximum simulation speed and bottlenecks can be readily identified using bus analysis. The interconnect architecture can be quickly adjusted and easily re-generated to remove these bottlenecks.

The bus simulators (delivered as part of a Bus Library) are available for multiple levels of abstraction and can incorporate transaction-level and RTL models, automatically building the necessary interfaces between the transaction domain and the signal domain. In this way, the designer can introduce RTL implementation models mixed into the transaction-level system one by one, resulting in huge verification performance benefits.

Programmers View (also referred to as LT, loosely timed) bus simulators are also available to dramatically increase the platform simulation performance for the purpose of running and debugging embedded software with transaction-level views of the hardware. To enable interoperability with peripherals that are developed based on Synopsys’ SystemC Modeling Library (SCML) at the Programmers View level, transactors are delivered with the Bus Libraries of the Platform Architect Models. The bus simulators are also compatible with emerging TLM standards from OSCI and OCP to enable maximum IP re-use.

Synopsys provides Bus Libaries, pre-instrumented with extensive analysis capabilities, for certain standard on-chip interconnects like ARM AMBA 2.0, ARM AMBA 3 AXI, Sonics SMX and IBM CoreConnect. Synopsys can also provide services to create bus simulators for your in-house interconnect specifications.

Peripheral Models
Synopsys TLM Modeling methodology based on Synopsys’ SystemC Modeling Library (SCML) enables reuse of peripherals for multiple design tasks and different communication protocols. These peripheral models can both be used for high speed SW development and architectural exploration in combination with the transactors delivered with the Synopsys Bus Libraries.

Based on this modeling methodology Synopsys has developed an extensive set of functionally accurate SystemC models for the ARM® PrimeCell® family. These models allow the designer to create and configure platforms and develop software early in the development process. On top of that Synopsys delivers a Generic IP Library (GIPL) with Platform Architect. This Generic IP Library consists of a base set of peripherals that are typically used in any platform. In addition, all models from the DesignWare System-Level library can be used with Platform Architect, including TLM representations of the DesignWare Interconnect IP.

Memory Subsystem Models
Memory subsystems are an increasingly important part of today's complex designs. Synopsys partners with IP vendors like ARM and Sonics to provide cycle accurate models of their memory controllers.

An extensive range of memory models is also available through Synopsys interface to Denali's Memory Modeler-Advanced Verification (MMAV); enabling the use of Denali models in the Synopsys Platform Architect simulation environment.

IP models are continuously being added to Platform Architect Models portfolio, please check the Synopsys website for the latest list of available IP and the full range of SystemC-based, electronic system-level design tools.