Language Synthesis

• Supports MATLAB Language from The MathWorks
• Simpler, easier way to create a working algorithm
• 50-100x smaller code than RTL
• Fewer bugs introduced into flow

Automated Fixed-point Conversion Tools

• Fast conversion of floating point M-code into fixed-point
• Rapid exploration and refinement of precision
• Eliminates recoding and re-verification into fixed-point models

Synthesizable Fixed-point High Level IP Model Library

• Eliminates writing of fixed-point models from scratch
• Faster verification at higher levels of abstraction
• Offers more control over results

High Level Synthesis Optimizations and Transformations

• Automatic system-wide pipeline insertion scheduling and resource sharing
• IP-aware micro architecture optimization
• Automatic loop unrolling, scheduling and pipelining
• Target-aware optimization for FPGAs and ASICs

Integrated ASIC Flow

• Automatic generation of RTL constraints and scripts for Design Complier
• Advanced timing estimation using Design Compiler
• Rapid architecture exploration of speed, area and power tradeoffs

Integrated FPGA Flow

• Automatic generation of RTL constraints and scripts for Synplify Pro / Synplify Premier
• Advanced timing estimation using Synplify Pro / Synplify Premier
• Optimized resource mapping to advanced FPGA devices such as hardware multipliers, MACS, adders, memories and shift registers
• Enables Rapid Prototyping

RTL Testbench Generation

• Automatic generation of text vectors and scripts for RTL verification in VCS

C-Model Generation for Software Development and System Validation

• Fast model creation for C-based verification
• Begin software development earlier using virtual prototypes

Automated Flow from MATLAB language and High-level IP to Optimized RTL
Using a unique constraint-driven fixed-point propagation methodology, Synphony HLS allows designers to quickly and intuitively derive fixed-point models from a synthesizable subset of high-level, floating-point MATLAB code. The Synphony HLS engine then synthesizes architecturally optimized RTL to meet area, speed and power goals. Synphony HLS allows designers to stay in their preferred algorithm modeling language, eliminating the need to re-code and re-verify models and enabling early system-level validation and verification.

High Level Synthesis from a Single Model
The Synphony HLS engine can synthesize optimized architectures for ASIC, FPGA, rapid prototyping or virtual platforms while maintaining coherent verification through all levels of the implementation flow. Given the user-specified target and architectural constrains, the Synphony HLS engine automatically optimizes at multiple levels by applying pipelining, scheduling and binding optimizations across language and model boundaries, including M-language, IP blocks and throughout the design hierarchy.

Synthesis of Optimized RTL Architectures for ASIC and FPGA
Synphony HLS includes a new advanced timing estimation capability that automatically utilizes Design Compiler for accurate information needed in automatic pipelining and rapid timing closure for a given ASIC technology.

Synphony HLS includes advanced timing and device-specific optimizations for a broad range of FPGA families from Actel, Altera, Lattice and Xilinx. This includes optimized mapping to hardware multipliers, memories, shift registers and other advanced hardware resources in today’s FPGA devices.

Rapid Prototyping Methodology for Early Algorithm Validation
With Synphony HLS and Synopsys’ technology-leading Confirma Rapid Prototyping solution, design teams can quickly create a pre-silicon prototype of their design and start high-performance algorithm validation and software development much earlier in the design cycle.

C-model Generation for Early Software Development and Fast System Validation
Synphony HLS complements C/C++ implementation, verification and embedded software development flows by making C-model creation a natural byproduct of the development flow. Synphony HLS generates fixed-point ANSI-C models that can be used in a variety of system simulation environments and virtual platforms including Synopsys’ Innovator, System Studio, VCS and SystemC flows. Synphony HLS enables C-based verification and validation to start much earlier in the design cycle.