High-level Modeling Library and IP
Included in the Synplify DSP solution is a set of functional blocks commonly used in DSP design such as filtering (FIR, IIR), transforms, math and CORDIC functions, signal operations, memories, and control logic. These functions leverage the powerful MATLAB and Simulink simulation environments from The MathWorks for fixed-point, vector, and multi-rate simulation, and they provide a high level of hardware and architectural abstraction.
High-level Synthesis for FPGAs
The Synplify DSP high-level synthesis (HLS) engine automatically creates architecturally optimized RTL implementations of models built out of the Synplify DSP IP library. Architectural optimizations can automatically be applied to the model which allow area, speed, and power tradeoffs to be quickly evaluated across a range of device technologies. Implementation verification is maintained by automatically providing RTL testbench simulation scripts. The Synplify DSP HLS engine includes advanced technology characterization features which enable high quality optimizations for Actel, Altera, Lattice and Xilinx FPGAs.
- High-level Synthesis for ASICs
- Adds ASIC technology support in addition to the FPGA devices above
- Enables powerful prototyping capabilities — the same Synplify DSP model can target both ASIC and FPGA
- Advanced features specifically for ASIC:
- ASIC technology characterizations used for DSP Synthesis optimizations
- Memory Extraction for flexible support of 3rd party memory IP
- RTL Resolution for better support of downstream synthesis tools
- Support for standard ASIC design flows like Synopsys Design Compiler
The Synplify DSP design flow provides a much more powerful methodology for IP development and management by enabling system designers to capture a single model that supports multiple implementation targets and flows. The high-level of abstraction, unified modeling environment, architectural optimization capabilities, and portability means designers can achieve much higher ROI from algorithm and system engineering efforts.
The Synplify DSP software offers a fast and concise way to capture and verify DSP algorithms. From a single high-level model, the DSP synthesis engine can automatically create RTL testbench scripts to verify the RTL implementation behaves exactly as the model. This verification flow is maintained for all types of architectural transformations and optimizations that are made during the DSP synthesis phase. Hardware engineers can more easily create comprehensive simulations at a high level and eliminate the tedious creation of logic-level stimulus or the error-prone translation of test vector data.