English
|
日本サイ ト
|
中文网站
|
SOLVNET
Home
Tools
Manufacturing
Events
Events
News
SST article: Analysis of TSV proximity effects in planar MOSFETs and FinFETs
SPIE ADVANCED LITHO
View and download Synopsys papers
WEBINAR
View our latest webinars
TCAD News
December edition now available
Wafer Focus Newsletter
Latest edition available
Contact us
News
MagnaChip Selects Synopsys' Proteus LRC for Lithography Verification
Synopsys Accelerates Adoption of FinFET Technology with Production-Proven....
Imec and Synopsys Expand FinFET Collaboration to 10 Nanometer Geometry
Synopsys and TSMC Enable Lithography Compliance Checking for 20nm
Synopsys Announces Adoption of its TetraMAX ATPG and Yield Explorer Tools by....
SSMC Selects Synopsys' Proteus LRC
GLOBALFOUNDRIES Selects Yield Explorer for Faster Yield Ramp
More
All Synopsys News
Articles
EUV OPC flow optimization for volume manufacturing
Faster Yield Ramp at Sub-100-nm Technologies Using Design-Centric Volume Diagnostics Approach
Accurate EUV lithography simulation enabled by calibrated physical resist models
Yield Metrology Looking at Systematic Failure
EDN: Design-centric yield management
EDN: Synopsys tries to organize its efforts in EDA multiprocessing
More
Datasheets
Camelot
CATS
IC WorkBench Edit/View Plus
IC Workbench Plus
Proteus
Proteus LRC
Proteus MetroKit
More
Success Stories
Photronics Relies on Synopsys for Photomask Manufacturing Solutions
More
Webinars
New Features & Updates: Sentaurus TCAD (H-2013.03)
Foundry-Fabless Collaboration Achieves Higher Yield, Faster Ramp
TetraMAX and Yield Explorer for Rapid Failure Analysis
Lithography Verification on Advanced Nodes with Proteus
Volume Diagnostics for Yield Ramp at Nanometer Nodes
More
Newsletters
Wafer Focus, Summer 2012
CATS News, Spring 2012
Wafer Focus, Fall 2011
CATS News, Spring 2011
Wafer Focus, Fall 2010
Wafer Focus, Spring 2010
CATS News, Spring 2010
More
Product Guide
SNUG
TCAD
© 2013 Synopsys, Inc. All Rights Reserved.
Contact us
|
Locations
|
Privacy
|
Legal