Synopsys Technical Program at SPIE Advanced Lithography 2014 


A fast triple-patterning solution with fix guidance
(Paper 9053-9)
Wednesday, February 26, 10:30 am – 12:20 pm

Authors: Weiping Fang, Synopsys, Inc. (USA); Peter De Bisschop, IMEC (Belgium); Marco A. Hug, Srini Arikati, Erdem Cilingir, Synopsys, Inc. (USA); Julien Mailfert, IMEC (Belgium) and Katholieke Univ. Leuven (Belgium); Kevin Lukas, Synopsys, Inc. (USA); Weimin Gao, Synopsys, Inc. (Belgium) and IMEC (Belgium)

Abstract: Logic manufacturers are increasingly looking towards a triple patterning solution for their 10nm node Metal1 layer, and possibly for Via0, and local interconnect layers as well. Given the nature of NP-completeness for the 3-colorability problem, a challenge is how to go beyond a standard cell to efficiently decompose a layout at a block or chip level. Unlike an odd loop in double patterning, a triple patterning coloring conflict can’t be represented in a single loop. Another challenge for triple patterning is then how to report errors that the user can effectively use to fix them. We have developed a triple patterning decomposition system to address both challenges. We believe this system is the first of its kind, both in terms of performance and in terms of useful error output.

A new integrated Monte-Carlo code for the simulation of high-resolution scanning electron microscopy images for metrology in microlithography
(Paper 9050-17)
Tuesday, February 25: 8:00 am – 10:00 am

Authors: Mauro Ciappa, Emre Ilgüsatiroglu, Alexey Y. Illarionov, ETH Zürich (Switzerland); Lars H. Bomholt Jr., Synopsys Switzerland, LLC (Switzerland)

Abstract: In order to keep pace with the relentless downscaling resolution imposed to metrology in the micro-lithography, a detailed physical understanding and modeling of SEM signal generation at the level of fundamental particle interactions and charge transfer, as well as an accurate description of the sample in the nanometer-scale are required. A new Monte Carlo code is presented that includes among others definition of arbitrary geometries with sub-nanometer resolution, high performance computing capabilities, trapped charge and electric field calculation, electron tracking in electrostatic field, and calculation of 3D dose distributions. Applications are proposed dealing with the synthesis of SEM images of models generated by mesoscale simulation and other approximation techniques.

Applying ILT mask synthesis for co-optimizing design rules and DSA model parameters
(Paper 9052-47)
Thursday, February 27, 1:35 pm – 3:35 pm

Author: Thuc Dam, Synopsys, Inc. (USA)

Abstract: During early stage development of a DSA process, there are many unknown interactions between design, DSA process, RET, and mask synthesis. The computational resolution of these unknowns can guide development towards a common process space whereby manufacturing success can be assured. This paper will demonstrate the use of existing Inverse Lithography Technology (ILT) to quickly co-optimize these multitude of parameters.

Combining lithography and etch models in OPC modeling
(Paper 9052-76)
Tuesday, February 25, 6:00 pm – 8:00 pm Poster Session

Authors: Lena V. Zavyalova, Lan Luan, Hua Song, Synopsys, Inc. (USA); Thomas Schmoeller, Synopsys GmbH (Germany); James P. Shiely, Synopsys, Inc. (USA)

Abstract: With constant shrinking of device critical dimensions (CD), the quality of pattern transfer in IC fabrication depends on the etch process and the exposure process fidelities, and the interaction of lithographic and etching processes is no longer negligible. Etch effect correction with accurate models has become an important component in optical proximity correction (OPC) modeling and related applications. It is now commonly accepted that the lithographic and etch effects should be modeled and corrected in a sequential and staged way: a resist (or lithographic) model should be created and used for lithographic effect compensation, and an etch model should be created and used for etch effect compensation. However, there can be various degrees of separation of these two modeling stages. In order to optimally capture the significant variation in the post-development resist patterns and post-etching patterns, it is helpful to integrate these two processes together for the OPC model calibration practice. In this paper, we analyze the integrated simulation approach in OPC modeling where the entire resist model information is made fully accessible in the etch modeling stage to allow the possibility of resist and etch co-optimization, e.g. through adjusting the resist model to optimally fit the etch data. Furthermore, the integrated simulation technique is integrated into a verification flow to simplify the conventional staged flow.

Experimental validation of rigorous, 3D profile models for negative-tone develop resists
(Paper 9052-11)
Tuesday, February 25: 1:30 pm – 3:00 pm

Authors: Weimin Gao, Synopsys, Inc. (Belgium); Ulrich Klostermann, Thomas Schmoeller, Synopsys GmbH (Germany); Kevin Lucas, Synopsys, Inc. (USA); Wolfgang Demmerle, Synopsys GmbH (Germany); Peter De Bisschop, Julien Mailfert, IMEC (Belgium). [9052-11]

Abstract: The extension of 193nm immersion lithography to the 14nm node and beyond directly encounters a significant reduction in image quality. One of the consequences is that the resist profile varies noticeably, impacting the already limited process window. Resist top-loss, top-rounding, T-top and footing all play vital roles in the subsequent etch process. Therefore, a reliable rigorous model with the capability to correctly predict resist 3D (R3D) profiles is acquiring higher importance. In this paper, we will present a calibrated rigorous model of a negative-tone develop resist. Resist profiles can be well simulated through focus and dose, and good matches to the experimental wafer data are validated. Such a model can not only provide early investigation of insights into process limitation and optimization, but can also complement existing OPC models to become R3D-aware in process development.

Improving 3D resist profile compact modeling by exploiting 3D resist physical mechanisms
(Paper 9052-32)
Wednesday, February 26, 3:30 pm – 5:30 pm

Authors: Yongfa Fan, Synopsys, Inc. (USA); Cheng-En R. Wu, Synopsys Taiwan Ltd. (Taiwan); Hua Song, Synopsys, Inc. (USA); Thomas Schmoeller, Synopsys GmbH (Germany)

Abstract: The useful depth of focus has become comparable to the resist film thickness as the 193nm immersion deep UV lithography technique is pushed to its resolution limit, with a consequence that the resist profiles may deviate from ideality. In some weak image areas, serious resist top loss or footing often occur, which, in turn, can result in killing defects in the subsequent etch processes. Since conventional 2D OPC modeling does not handle 3D resist profile, the phenomenon and practical needs have spurred extensive research activities in the past few years to simulate 3D resist profiles with compact models for full-chip OPC applications. The reported approaches more or less borrow the physical mechanisms in rigorous optical lithography models which include 3D resist profile simulation but runs too slow for full-chip applications. A simple approach is to build individual 2D models at different image depths either based on actual wafer measurement data or virtual simulation data by an already calibrated rigorous lithography model. Application of any of the individual 2D models to downstream OPC/LRC tools is straightforward. However, the relevant image depths need be determined in advance due to the discontinuity nature of the methodology itself. The physical commonality among the individual 2D models may deviate from each other as well during the separate calibration processes. A second approach assumes that the 3D resist profile formation is dominated by optical image variation across the resist film thickness while resist material properties specific to height position are ignored. Despite its simplicity, it’s prediction on 3D resist profile may be inaccurate when resist materials property is not uniform, especially when surface effects are not negligible. The aforementioned drawbacks were addressed in this work by adopting more physical simulation mechanisms from rigorous simulation methodologies while keeping the model form compact for full-chip applications. To that end, the bulk image is calculated by using one set of retained Hopkins kernels. Optical intensity can be assessed at any image depth without accuracy compromise. With an accurate bulk image, a simplified model for chemically amplified resist is used to simulate resist behavior. The resist models contains acid generation, acid-base neutralization, lateral and vertical diffusion. Boundary conditions at the resist interface used to account for surface effects. The model is formulated in a continuous form so that a model slice at any image depth is readily available to use after calibration. While the calibration data is collected with discrete image planes, all planes are calibrated simultaneously using one set of resist parameters to guarantee physical commonality among them. Moreover, the calibration is done stepwise carefully to ensure the optical part to account for optical effects and resist model to account for resist effects. The calibrated model is compared against the rigorous model, showing that critical resist profile failures can be successfully predicted. In addition to regular model validation process, a measure of resist model separability is used to judge resist model quality. It is shown that the resist model can be carried to a different lithography process with same resist setup but a different illumination source without model noticeable accuracy degradation. The work shows that the accuracy of compact 3D resist models is improved by adopting more physical resist mechanisms.

Numerical analysis for resist profile after thermal process in display manufacturing
(Paper 9051-63)
Wednesday, February 26, 6:00 pm – 8:00 pm Poster Session

Authors: Vitaliy Domnenko, Synopsys SPb, LLC (Russian Federation); Sangmin Shin, Jonghyoek Ryu, Sung Won Choi, Hyunwoo Cho, Samsung Display Co., Ltd. (Korea, Republic of); Eun-Soo Jeong, Synopsys Korea Inc. (Korea, Republic of); Hans-Jurgen Stock, Synopsys GmbH (Germany); Jung-Hoe Choi, Synopsys Korea Inc. (Korea, Republic of). [9051-63]

Abstract: The screen size growth of mobile displays is accompanied with the drastically increased resolution. A display should have high pixel resolution to meet demanding readability and legibility expectations. One of the important process steps is post-development hardbake, where resist reflow is used to tune the final profile which influences follow-up processes. The model presented in this paper is based on lattice-Boltzmann method. Simulated resist profile dynamics with time is analyzed in dependency of material parameters. Validation against experimental data shows good model consistency and predictability, demonstrating the benefit of simulation in process development and optimization.

Proteus inverse lithography technology: ILT where it is needed
(Paper 9052-87)
Tuesday, February 25, 6:00 pm – 8:00 pm Poster Session

Authors: Mindy Lee, Guangming Xiao, Kevin Lucas, Synopsys, Inc. (USA); Woo J. Sim, Ho Sun Cha, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)

Abstract unavailable