September 10 - 12, 2013
Synopsys Booth #303
Exhibit Dates and Hours
Tuesday, September 10: 10:00 AM-4:00 PM and 6:00 PM-7:30 PM
Wednesday, September 11: 10:00 AM-4:00 PM
Synopsys is a world leader in EDA and IC manufacturing software and has the industry's most comprehensive solution from design to silicon. Synopsys’ approach ensures an intelligent use of technology and data throughout the flow. Speak with experts about how Synopsys’ production-proven mask synthesis, lithography simulation, and leading mask data preparation can provide superior turnaround time, cost of ownership, and accuracy of results at advanced technology nodes.
Meetings and Product Updates Overview
Mask Data Preparation – CATS
CATS is the industry’s most widely used solution for mask data preparation. During this meeting, Synopsys will present technical details and results on the latest developments that enable CATS to offer unmatched quality-of-results and fastest throughput for mask manufacturing. It will also provide an opportunity for customers and partners to participate in CATS roadmap discussions with the Synopsys team.
Advanced OPC/RET – Proteus / Sentaurus Lithography
Proteus OPC has been providing industry-proven scalability and lowest cost of ownership for over a decade, and with the well-established Proteus Pipeline Technology (a unique concept of concurrent processing of all manufacturing applications), foundries and IDM’s have recognized additional performance and cost savings benefits. Also, great strides have been made to increase accuracy in manufacturing through the integration of Proteus and Sentaurus Lithography, where rigorous simulations are seamlessly utilized to supplement correction and verification flows. The Proteus team would like to meet with you to discuss the latest updates in our continual progression towards accuracy, runtime, and cost-of-ownership improvements.
Meet with Synopsys
If you are planning to attend SPIE Photomask and you’d like to schedule an on-site meeting or product update with Synopsys, please contact your sales rep or send an email to firstname.lastname@example.org. Include your business title, company name, office and mobile numbers, names of all participants and the topic you’d like to discuss.
Session 6: Simulation, OPC, and Mask Data Preparation II
Date: Tuesday 10 September
Time: 3:40 PM - 4:40 PM
An accurate ILT-enabling mask 3D full chip modeling for all-angle patterns - (Paper 8880-15)
Author(s): Hongbo Zhang, Qiliang Yan, Ebo H. Croffie, Lin Zhang, Yongfa Fan, Synopsys, Inc. (United States)
Mask3D effect is a necessary factor for full chip simulation/OPC process, as well as the ILT process. However, the existing Mask3D model cannot support well for the all-angle patterns well and thus reduce the quality of the mask synthesis process and shrink the process window due to the miss of ILT. We propose a novel modeling framework to enable all-angle patterns with very competitive runtime speed and high accuracy. The model can be successfully combined with ILT and our experimental results demonstrate strong prediction power and high runtime efficiency for both normal incidence and off-axis optical sources and various types of 1D and 2D patterns.Simulation study of CD variation caused by field-edge effects and out-of-band radiation in EUVL - (Paper 8880-16)Author(s): Weimin Gao, Synopsys, Inc. (Belgium); Ardavan Niroomand, Micron Technology, Inc. (United States); Gian F. Lorusso, IMEC (Belgium); Robert Boone, Kevin Lucas, Synopsys, Inc. (United States); Wolfgang Demmerle, Synopsys GmbH (Germany)
The “black border” (BB) effect in EUVL significantly impacts on CD uniformity. We present a method of modeling the BB effect using rigorous simulations. Firstly, the flare map is created by using the point spread function of the scanner and convolving with the pattern density map of the mask. Secondly, an additional “flare level” is introduced on top of the flare map to account for the BB effect. The simulation results match well the experiments. Using simulation we can also determine the OoB effect. It demonstrates that the impact of BB and OoB effects on CDU can be well predicted.
Session 7: Patterning and Double-Patterning Technology
Date: Tuesday 10 September
Time: 4:40 PM - 5:20 PM
Color balancing for triple-pattern lithography with complex designs - (Paper 8880-17)
Author(s): Haitong Tian, Univ. of Illinois at Urbana-Champaign (United States); Hongbo Zhang, Synopsys, Inc. (United States); Zigang Xiao, Martin D. F. Wong, Univ. of Illinois at Urbana-Champaign (United States)
Triple patterning lithography (LELELE) has been widely recognized as one the most promising alternatives for 14/10nm technology node. However, none of the previous works addresses the global and local coloring balancing issue for both simple and complex designs. We propose an efficient and robust approach which guarantees to find a color balancing decomposition while achieving the optimal number of stitches for complex designs. Both global color balancing scheme and local color balancing scheme are addressed. For the largest benchmark with over 10 million features, experimental results show that the new approach achieves almost perfect color balancing with reasonable runtime.
Date: Tuesday 10 September
Time: 6:00 PM - 7:30 PM
Model-driven design target movement to resolve design hot spots through image quality enhancement - (Paper 8880-68)
Author(s): Sung-Woo Lee, Synopsys Korea Inc. (Korea, Republic of); Thomas Cecil, Guangming Xiao, Mindy Lee, Synopsys, Inc. (United States); Jung-Hoe Choi, Seung-Hee Baek, Synopsys Korea Inc. (Korea, Republic of); Jin-Hyuck Jeon, SK Hynix, Inc. (Korea, Republic of); Dave H. Kim, Synopsys, Inc. (United States); Chan-Ha Park, SK Hynix, Inc. (Korea, Republic of); Kevin Lucas, Synopsys, Inc. (United States)
No abstract available
Mask topography effect characterization by rigorous model and its implementation for full-chip simulation - (Paper 8880-76 )
Author(s): Hongbo Zhang, Qiliang Yan, Ebo H. Croffie, Lin Zhang, Yongfa Fan, Jing Xue, Synopsys, Inc. (United States)
Recent study has shown the significant improvement by using emulated data for compact OPC model optimization. The basic idea is to use rigorous model as a guidance for the compact model construction, which can both reduce the amount of input empirical data and increase the flexibility and reliability of the fitting process in the compact model. We further extend this idea to enable an efficient Mask3D model which has both high efficiency and accuracy at the full chip level implementation.
An efficient and accurate full-chip mask 3D model for off-axis illumination with effective mask rigorous library - (Paper 8880-78)
Author(s): Hongbo Zhang, Qiliang Yan, Lin Zhang, Ebo H. Croffie, Peter D. Brooker, Qian Ren, Yongfa Fan, Synopsys, Inc. (United States)
Off-axis illumination is a necessary factor that will impact the performance of Mask3D model. In this paper, we propose a novel method with an effective mask rigorous library to efficiently and accurately capture the behavior of OAI source together with Mask3D effect. The experimental results demonstrate the runtime is the same as with the normal incident optic source and the CD RMS for 2D pattern can be as low as <1nm.
AF printability check with a full-chip 3D resist profile model - (Paper 8880-89)
Author(s): Cheng-En R. Wu, Synopsys Taiwan Ltd. (Taiwan); Hua Song, Synopsys, Inc. (United States)
In this work, we propose a single 3D resist model that takes z-diffusion effect into account by applying the solution of 1D diffusion equation that the analytic forms can be derived for certain boundary conditions. All models from all imagedepth are calibrated in a single cost function so that they share common free parameters and threshold. The equivalent z-diffused TCC can be pre-calculated so the 3D resist model offers a more physical approach but adds no runtime concern on the OPC and verification applications. The predicted resist cross-section profiles from our test pattern are compared with rigorous SLITHO simulations and show good matching results between them. The demonstration of the AF printing predicted directly from the cross-section profile indicates the success of our resist 3D model.
Session 16: Mask Manufacturing, and Yield and Mask Business
Date: Thursday 12 September
Time: 10:50 AM - 12:10 PM
DSA template mask determination and cut redistribution for advanced 1D gridded design - (Paper 8880-44)
Author(s): Zigang Xiao, Yuelin Du, Martin D. F. Wong, Univ. of Illinois at Urbana-Champaign (United States); Hongbo Zhang, Synopsys, Inc. (United States)
Directed self-assembly (DSA) technology has already demonstrated its capability for isolated and grouped contact/via pattern for 1D gridded design. If we reverse the resist tune, this technique can also be used to implement the cut printing. However, for this purpose, we need to redistribute the cuts by extending the real wires to form the desired cut distribution for template mask making. Based on this assumption, in this work, we propose an algorithm to shift the original cuts such that they form groups of non-conflict DSA template to have a valid template mask, while the overall cut movement is minimized.