The Evolution of EDA Alongside Rapid Silicon Technology Innovation
Monday, February 25, 9:10 to 9:50 am
Convention Center Hall 3
Authors: Howard Ko, Senior VP and General Manager, Synopsys' Silicon Engineering Group
Abstract: The overall product design and manufacturing flow needed to create a new advanced semiconductor device is one of the most economically successful and most complex industrial ecosystems in the world. The ongoing economic success is especially amazing when one considers the enormous changes which occurs in this complex ecosystem every technology generation. SPIE attendees know full well the many important difficulties and challenges involved in continuing the rapid pace of cost-effective lithography and silicon process development. Just as critical, however, are the challenges which designers and EDA suppliers face to modify and re-architect their design flows and design tools to best incorporate the outcomes of this rapid technology improvement. The goal of this talk is to provide high level insight into the continuing evolution which the EDA industry has done and must continue to do in order to keep pace with the hectic pace of silicon technology innovation.
3D resist profile modeling for OPC applications
February 28 • 10:40 - 11:00 AM
Authors: Yongfa Fan, Synopsys, Inc. (United States); Koh K. Kit, Globalfoundries (China); Qing Yang ; Wolfgang Hoppe, Bernd Kuechler, Synopsys GmbH (Germany); Puvan Perampalam; Makoto Miyagi, Synopsys, Inc. (United States); Thomas Schmöller, Synopsys GmbH (Germany)
Abstract: While critical lithographic feature size diminishes, resist profile can vary significantly as image varies. As a consequence, the final etch results are becoming more dependent on 3D resist profile rather than only a simple 2D resist image as an etch mask. Therefore, it has become necessary to build resist profile information into OPC models, which traditionally only contain 2D information in the x-y plane. At the same time, rigorous lithographic simulators are capable of modeling 3D resist profiles on a small chip area. In this work, one approach is investigated to account for 3D resist profile characteristics in full-chip OPC models with the assistance of. With measurement data collected from experimental wafers, a rigorous resist model is first calibrated and verified. Then individual compact models are built to match the rigorous resist model profile at specified resist heights. The calibrated compact model for bottom resist line width corresponds to a conventional OPC model while resist profile is described by multiple models specified for certain resist heights, with each model being in the form of conventional compact models. In practice, the bottom model along with one or two models at critical heights are usually sufficient to detect sites where etch results become sensitive to resist profile. It has been found that the rigorous resist profile model can be well matched by the suggested compact models. For a quick application demonstration, hot spots of the etch results in the test case have been shown to be successfully captured by the calibrated compact models.
7nm node EUV predictive study of mask LER transference to CD variance
February 27 • 6:00 - 8:00 PM
Authors: Deniz Civay, Thomas I. Wallow, Yuansheng Ma, Harry J. Levinson, GLOBALFOUNDRIES Inc. (United States); Joachim Siebert, Eva Nash, Ulrich K. Klostermann, Synopsys GmbH (Germany)
Abstract: The transition into smaller nodes has resulted in stringent CD tolerance requirements and the role of mask LER in that budget is not well understood. The critical variables associated with mask LER were explored with the goal of establishing mask requirements based on wafer requirements. A systematic study of the impact of mask LER correlation length, critical exponent and standard deviation of the line edge on the printability of 7nm node line/space (L/S) and contact holes (CH) in extreme ultraviolet lithography has been simulated.
Avoiding wafer-print artifacts in spacer is dielectric (SID) patterning
February 27 • 4:30 - 4:50 PM
Authors: Gerard Luk-Pat, Benjamin D. Painter, Alexander Miloslavsky, Synopsys, Inc. (United States); Peter De Bisschop, IMEC (Belgium); Adam Beacham, Synopsys, Inc. (Canada); Kevin Lucas, Synopsys, Inc. (United States)
Abstract: For patterning the upper Metal layers of the 14 nm node, Spacer Is Dielectric (SID) Patterning is the leading candidate. Compared to Litho-Etch-Litho-Etch Double Patterning, SID has lower line-width roughness, tighter line-end spacing, and lower sensitivity to overlay errors. However, SID places more restrictions on design, and creates wafer-printing artifacts. These printing artifacts arise because SID uses a subtractive trim etch to create “negative contours,” which are very different from the positive contours of single-exposure patterning. In this work, we show the origin of these spurs, and focus on modifying the decomposition to avoid or mitigate them.
Compact OPC model optimization using emulated data
February 27 • 1:40 - 2:00 PM
Authors: Artak Isoyan, Synopsys, Inc. (United States); Thomas Mülders, Synopsys GmbH (Germany); Lawrence S. Melvin III, Synopsys, Inc. (United States)
Abstract: In this work we present an optical proximity correction (OPC) compact model methodology that requires a reduced quantity of empirical (wafer) data for model calibration, and enables full and predictable extrapolation to any process condition within a focus-exposure matrix.
Design-based metrology for development and manufacturing applications
February 26 • 6:00 - 8:00 PM
Authors: Peter D. Brooker, Synopsys, Inc. (United States); Shimon Levi, Applied Materials (Israel); Sylvain Berthiaume, Synopsys, Inc. (Canada); William A. Stanton, Travis Brist, Synopsys, Inc. (United States)
Abstract: This work presents how the combination of EDA and CDSEM tools enable development and manufacturing engineers to collect CDSEM data of a large diversity of features and contexts seamlessly for OPC model calibration and validation, process development, and inline manufacturing monitoring. We will present the application and results of a solution proposed in a previously published paper1 and then review the benefits of enabling development and manufacturing engineers to make metrology-related decisions within their environments. Finally, new applications for automated CDSEM recipe generation and data collection will be discussed.
1. Automated SEM recipe generation for OPC applications [8324-62] S. Berthiaume, T. Brist, P. Brooker, W. Stanton, B. Ward, S. Levi, A. Siany
Evaluation of cost-driven triple-patterning lithography decomposition
February 27 • 11:20 - 11:40 AM
Authors: Haitong Tian, Univ. of Illinois at Urbana-Champaign (United States); Hongbo Zhang, Synopsys, Inc. (United States); Martin D. F. Wong, Univ. of Illinois at Urbana-Champaign (United States)
Abstract: The photolithography technology is approaching its bottleneck at the current 193nm ArF immersion technology. Triple patterning lithography (TPL) is one of the major options for 14 nm or 10 nm technology node. In reality, the no-print and the best-print scenarios in TPL can never be separated by a clear constant spacing distance dmin. The conventional spacing rule with a constant number is way too simple. In this paper, we will utilize the optimal result from our previous work to re-evaluate the conventional minimum spacing rule and propose an investigation on a novel cost-driven triple patterning decomposition process.
The impact of realistic source shape and flexibility on source-mask optimization
February 27 • 9:00 - 9:20 AM
Authors: Hajime Aoyama, Yasushi Mizuno, Noriyuki Hirayanagi, Nikon Corp. (Japan); Hiro Izumi, Keiichi Tajima, Nihon Synopsys G.K. (Japan); Joachim Siebert, Wolfgang Demmerle, Synopsys GmbH (Germany); Tomoyuki Matsuyama, Nikon Corp. (Japan)
Abstract: We developed Intelligent Illuminator, which has many degrees of adjustment freedom of intensity distribution in source images for enabling SMO solution and pupilgram modulation for optical proximity effect matching between exposure tools. Since the actual illuminator has some source constraints such as pixel number, intensity blur of the pixel source and pupil fill ratio, the SMO engine should be able to take into these parameters in the optimization for more practical solutions. In this paper, we describe the impact of the source constraints of exposure tools and the validation of the effect of optimization considering the constraints in a use of Proteus SMO.
Improved SADP decomposition for SID process with model-based verification
February 28 • 8:20 - 8:40 AM
Authors: Yuelin Du, Univ. of Illinois at Urbana-Champaign (United States) and Synopsys, Inc. (United States); Hua Song, James P. Shiely, Synopsys, Inc. (United States); Martin D. F. Wong, Univ. of Illinois at Urbana-Champaign (United States)
Abstract: Lacking a realistic verification model, all the previous 2D SADP decomposition algorithms have a common assumption that the printing contour of mandrel/trim and the spacer shape are rectilinear polygons. However, even with perfect OPC, the spacer shape still gets rounded at the mandrel corners, which causes severe residue artifacts on the printed target patterns. In this paper, a realistic SADP verification model is developed, based on which two types of artifacts are identified due to spacer’s corner rounding property. Then an improved SADP decomposition strategy is developed to remove the residue artifacts through proper mandrel assignment and mandrel merging.
Mask compensation for process flare in 193nm very low-K1 lithography
February 26 • 4:10 - 4:30 PM
Authors: Jeonkyu Lee, Taehyeong Lee, Chunsoo Kang, Jungchan Kim, Jaeseung Choi, Chan-Ha Park, Hyun-Jo Yang, Dong Gyu Yim, SK Hynix, Inc. (Korea, Republic of); Jung-Hoe Choi, Synopsys Korea Inc. (Korea, Republic of); Irene Su, Synopsys Taiwan Ltd. (Taiwan); Hua Song, Synopsys, Inc. (United States); Mun-hoi Do, Synopsys Korea Inc. (Korea, Republic of); Yongfa Fan, Anthony C. Wang, Synopsys, Inc. (United States); Sung-Woo Lee, Synopsys Korea Inc. (Korea, Republic of); Kevin Lucas, Synopsys, Inc. (United States)
Abstract: In this paper, we provide examples and discussion of how optical and chemical flare related effects are becoming more problematic, especially at the boundaries of large, dense memory arrays. We then introduce a practical correction method for these systematic effects which reuses some of the recent long range effect correcting OPC techniques developed for EUV pattern correction (such as EUV flare). We next provide analysis of the benefits of these OPC methods for optical or chemical flare issues in 193nm lithography very low K1 lithography. Finally, we summarize our work and briefly mention possible future extensions.
Role of 3D photoresist simulation for advanced technology nodes
February 28 • 2:40 - 3:00 PM
Authors: Aravind Narayana Samy, Rolf Seltmann, Frank Kahlenberg, Jessy Schramm, GLOBALFOUNDRIES Dresden Module Two, GmbH& Co. KG (Germany); Bernd Kuechler, Ulrich K. Klostermann, Synopsys GmbH (Germany)
Abstract: We demonstrate the significance of 3D resist model in advanced technology nodes for ORC hotspot verification due to resist profile’s impact on etch resistivity and post etch results. The main focus is given to high quality metrology data in building a successful 3D resist model. We want to show huge reduction in the calibration effort and hence the time in a productive environment due to the clean metrology data. We would like to present our excellent validation results for both metrics using complete SEM CD, SEM images and wafer cross sections as a proof that the model is not over-fitted due to the reduced dataset. Resist model portability is also shown by validation and application of the model to a second process with significantly different optical settings and still achieving the same quality as for the original calibrated process.
Triple patterning with polygon stitching: scalability and compliance for metal 1 at the 14nm node
February 26 • 11:50 AM - 12:10 PM
Authors: Christopher M. Cork, Synopsys SARL (France); Alexander Miloslavsky, Yong Li, Kevin Lucas, Synopsys, Inc. (United States)
Abstract: For Local Interconnect and Metal 1 layers on the 14 nm node, triple patterning technology (TPT), using three litho-etch sequences (LELELE), is the favored option. Metal layers offer challenges and opportunities for TPT. One challenge is design compliance: the third color can improve compliance over double patterning but creating compliance errors remains easy. Another challenge is scalability, with prohibitive computation times for networks beyond a few thousand nodes. One opportunity is stitching polygons but this worsens scalability. This paper identifies non-compliant layout configurations, looks at different approaches to TPT decomposition, and compares their scalability and effect on packing density.