PrimeTime - Static Timing Analysis 

Smarter, Golden Signoff 

Synopsys' PrimeTime static timing analysis tool provides a gold-standard, trusted signoff solution for timing, signal integrity, power and variation-aware analysis. PrimeTime delivers HSPICE® accurate signoff analysis that helps pinpoint problems prior to tapeout, thereby reducing risk, ensuring design integrity, and lowering the cost of design. This industry gold-standard improves your team’s productivity by delivering fast turnaround time (TAT) to shave precious weeks from development schedules for large, medium and small designs, while ensuring first-pass silicon success through greater predictability and the highest accuracy.

 
The PrimeTime Suite includes:
PrimeTime
  • Core static timing analysis
  • Multi-scenario analysis
  • PrimeTime SI
  • Crosstalk delay and signal integrity analysis
  • Constraint consistency checking
  • Hierarchical timing analysis
  • PrimeTime ADV
  • Physically-aware ECO guidance for timing, DRC and power recovery
  • Parametric on-chip variation (POCV)
  • Distributed hierarchical analysis
  • PrimeTime PX
  • Static and Dynamic Power Analysis
  • Key Benefits
  • HSPICE-accurate results minimize over-design
  • Integrated design environment improves productivity
  • Fast turn-around time speeds analysis and signoff
  • High capacity approach reduces hardware costs
  • Multi-scenario ECO accelerates timing closure and power recovery
  • Fast, flexible, timing constraint consistency checking
  • Accurate analysis of latch based designs
  • Latest on-chip variation modeling technology accelerates timing signoff
  • Complete solution ensures comprehensive signoff
  • Download Datasheet

    Advanced Waveform Propagation

    With smaller geometry process nodes and lower operating voltages, comes the opportunity for digital signals to exhibit behaviors once only associated with analog design. Waveforms no longer look like a predictable sloping curve. PrimeTime can model the Miller effect and other distortions seen at low and ultra-low voltages, and FinFET nodes with its advanced waveform propagation (AWP) technology. This technology is critical to maintain the gold-standard, accurate correlation to HSPICE for timing signoff that PrimeTime users have come to expect.

    Parametric On-Chip Variation

    On-chip variation (OCV) effects continue to increase with shrinking geometry nodes and lower voltages. Applying a flat global margin across the entire chip can lead to overdesign, reduced design performance, and longer timing closure schedules. While the PrimeTime Advanced OCV (AOCV) technology takes advantage of improved device-level variation modeling techniques to provide the right balance between accuracy and performance for planar process node designs, the more advanced Parametric OCV (POCV) provides the necessary technology to accurately analyze FinFET designs.

    HyperScale

    When TAT and capacity are critical, HyperScale is a must. PrimeTime HyperScale technology brings smarter, hierarchical timing analysis to mainstream designs, allowing teams to take advantage of a more efficient block-level methodology and smaller, more readily available machines. This technology extends PrimeTime static timing analysis to support designs beyond 500 million instances, while delivering 2 to 5X faster runtimes for the full chip timing analysis using 2 to 5X smaller memory footprint, compared with flat analysis. PrimeTime HyperScale technology enables hierarchical STA by performing accurate block level timing analysis in the context of the top-level. This technology offers faster top and block timing convergence, timing reuse, and scalability to complete daily analysis on any size designs.

    Multi-scenario Analysis

    PrimeTime offers several technologies to accelerate both the analysis and debug of multi-scenario designs. Going beyond multi-scenario analysis, PrimeTime mode merging and simultaneous multi-voltage aware analysis (SMVA) actively work to reduce the number of scenarios to be analyzed. This allows users to reduce the hardware resources and turnaround time for multi-scenario analysis, while maintaining signoff quality timing correlation. Distributed Multi-Scenario Analysis (DMSA) and Interactive Multi-Scenario Analysis (IMSA) allow users to efficiently setup and debug multi-scenario runs.

    ECO Guidance

    PrimeTime ECO guidance technology uses signoff-driven analysis to efficiently identify ECO changes for timing and DRC fixes at the block or chip level, shortening tape-out schedules by weeks. Multi-scenario, physically-aware ECO guidance reduces the time and iterations required to reach timing closure on congested designs. PrimeTime can provide critical optimizations for clock trees, noise reduction, and spare cell ECOs, while using 5X less memory and compute resources. PrimeTime ECO can take advantage of positive timing slack for leakage power reduction opportunities. In addition, PrimeTime supports incremental ECO changes within the Galaxy Platform tool flow, further reducing turnaround time.

    Timing Constraint Consistency

    The rapid increase in design size and complexity, the advent of hierarchical block-level analysis, as well as the widespread reuse of IP design blocks, has led to a major increase in the size and complexity of timing constraint specification files. Not only are the constraints getting more complex, it is important to make sure the constraints are consistent across the design, across the hierarchy, and across the implementation flow. Ensuring high-quality timing constraints is paramount to efficient design implementation, especially during handoffs between teams. Incomplete, inconsistent or conflicting constraints can cause optimization, implementation and analysis tools to run ineffectively or to fail to converge. To address this challenge, PrimeTime provides a comprehensive set of rule checks designed to ensure constraint consistency and to maximize the efficiency of implementation and timing analysis.

    What Is a PrimeTime Special Interest Group (SIG)?
    The Synopsys PrimeTime Special Interest Group (SIG) is an active community for all PrimeTime users and design engineers who want to stay connected with the latest developments in the field of Static Timing Analysis (STA). Increasing design size and complexity are putting tremendous pressure on design schedules. STA is a key technology used throughout the design process to accelerate design closure. As STA technology rapidly evolves, the PrimeTime SIG helps design teams stay abreast of the latest developments to help maximize their effectiveness and throughput.

    PrimeTime SIG 2016 Events

    PrimeTime SIG at SNUG Japan 2016
    Work Smarter with Advanced Signoff Technology
    September 9, 2016 Luncheon

    PrimeTime SIG at SNUG India 2016
    Work Smarter with Advanced Signoff Technology
    July 13, 2016 Reception

    PrimeTime SIG at DAC 2016
    Work Smarter with Advanced Signoff Technology
    June 12, 2016 Dinner

    PrimeTime SIG 2015 Events

    PrimeTime SIG at SNUG Japan 2015
    Maximize Productivity with Advanced Signoff-driven ECO Technology
    September 4, 2015

    PrimeTime SIG at SNUG India 2015
    Maximize Design Productivity with Advanced Signoff Technologies
    June 24, 2015 Reception

    PrimeTime SIG at DAC 2015
    Maximize Design Productivity with Advanced Signoff Technologies
    June 8, 2015 Dinner

    PrimeTime SIG 2014 Events

    PrimeTime SIG at SNUG Japan 2014
    Accelerating Timing Closure with Advanced Technologies
    Sept 19, 2014 Luncheon

    PrimeTime SIG at SNUG Taiwan 2014
    Accelerating Timing Closure with Advanced Technologies
    Sept 2, 2014 Afternoon Tea

    PrimeTime SIG at SNUG India 2014
    Accelerating Timing Closure with Advanced Technologies
    June 25, 2014 Reception

    Primetime SIG at DAC 2014
    Accelerating Timing Closure with Advanced Technologies
    June 2, 2014 Dinner

    PrimeTime 2016 Webinar Series

    Synopsys and ARM Experts Review Smart Constraint Management Practices for Efficient Timing Closure
    In this Webinar, Synopsys and ARM discuss accelerating timing closure by implementing timing constraint best practices. ARM kicks off the webinar with a comprehensive discussion of the best practices they recommend to their customers, covering areas such as PrimeTime constraint interpretation, clock constraint development and constraint management during the project life-cycle. Synopsys then outlines several constraint analysis techniques in PrimeTime SI that quickly confirm that these best practices are used.

    English | Simplified Chinese | Traditional Chinese

    Reduced-Resource ECO Lowers Memory Usage by 5X
    In this webinar, Synopsys discusses how a new PrimeTime ECO technology helps manage compute resource requirements by specifically targeting the parts of the design requiring ECO fixes. This technology has allowed PrimeTime ECO users to reduce the memory required to complete ECO closure by 5X while retaining the gold-standard quality of results expected from PrimeTime.

    English | Simplified Chinese | Traditional Chinese


    PrimeTime 2015 Webinar Series

    Using PrimeTime POCV to Improve Productivity and PPA in FinFET Designs – the NVIDIA Experience
    Synopsys will review the PrimeTime POCV technology that helps designers reduce design margins in FinFET designs, and you will learn about NVIDIA’s latest FinFET tapeout experience with PrimeTime POCV.

    STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95%
    STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.

    Multiply-instantiated Module (MIM) Timing Closure with PrimeTime ECO – with Samsung case study
    Join Synopsys as they discuss the fastest path to timing closure for MIM based SoC designs with PrimeTime ECO technology. A Samsung case study will show the benefits of a MIM ECO flow.


    PrimeTime 2014 Webinar Series

    Samsung Saves 20% Total Power on FinFET Designs with PrimeTime Signoff-driven ECO
    Join Synopsys as they discuss physically-aware ECO power recovery for advanced designs. Learn how Samsung reduced total power by 20% using PrimeTime ECO’s latest power recovery technology.

    Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow
    Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16 nm technology node and its impact to extraction and timing analysis. Learn about the latest developments in StarRC and PrimeTime that are V1.0 certified by TSMC to signoff your 16 nm designs.

    PrimeTime Cross-Clocking Reporting

    PrimeTime Cross-Clocking ReportingLearn how to avoid timing surprises due to unexpected timing paths when your designs continue to add more clocks and more IP.
    PrimeTime Cross-Clocking Reporting
    Runtime: 4:56 min.  Share This


    PrimeTime Physically-Aware ECO with On-Route Buffering

    PrimeTime Physically-aware ECO with On-route BufferingLearn how to accelerate your timing closure without disrupting the physical design or DRC fix rate
    PrimeTime Physically-aware ECO with On-route Buffering
    Runtime: 4:14 min.  Share This


    Access PrimeTime GCA Features During Timing Analysis

    Access PrimeTime GCA Features During Timing AnalysisLearn how PrimeTime GCA can be used to analyze constraint errors during timing analysis
    Runtime: 2:20 min.  Share This


    Fixing ECOs with PrimeTime

    Fixing ECOs with PrimeTimeLearn how PrimeTime ECO can save you weeks of effort in timing closure with multi-scenario ECO fixing, and how PrimeTime can reduce the complexity of multi-scenario analysis by providing instant visibility to all scenarios in a single view.
    Runtime: 7:53 min.  Share This


    Faster Debug: Filter-driven Schematic Highlighting

    Faster Debug: Filter-driven Schematic HighlightingLearn the most effective way to find objects in PrimeTime schematics.
    Runtime: 2:24 min.  Share This


    Faster Debug: The PrimeTime Path Analyzer

    Faster Debug: The PrimeTime Path AnalyzerLearn how the Path Analyzer can be used to quickly review and categorize large numbers of timing paths.
    Runtime: 3:39 min.  Share This


    Faster Debug: Selective Schematic Abstraction

    Faster Debug: Selective Schematic AbstractionLearn how to easily reduce complexity and accelerate debug with the PrimeTime schematic.
    Runtime: 2:05 min.  Share This


    Simultaneous Multi-Voltage Aware Timing Analysis

    Learn how PrimeTime's Simultaneous Multi-Voltage Aware (SMVA) Analysis helps you avoid the accuracy and runtime compromises normally associated with timing signoff of multi-voltage designs.
    Runtime: 10:41 min.  Share This

    Debugging Clock Problems with PrimeTime SI

    Learn about the options available in PrimeTime SI to identify and debug clock issues that can prevent timing closure.
    Runtime: 8:36 min.  Share This

    Clock Constraint Analysis with Constraint Analyzer

    Learn how you can easily get up and running with Galaxy Constraint Analyzer, and quickly identify critical clock constraint problems that could put your signoff at risk.
    Runtime: 10:16 min.  Share This

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