The Synopsys PrimeTime suite includes PrimeTime, PrimeTime SI, PrimeTime PX and PrimeTime VX. Anchored by the most trusted and advanced static timing signoff solution for gate-level designs, the PrimeTime suite offers comprehensive signal integrity analysis, statistical timing analysis and full chip power analysis in a single integrated environment.
- Key Benefits:
- HSPICE-Accurate Results Minimize Over-Design
- Integrated Design Environment Improves Productivity
- Fast Turn-around Time Speeds Analysis and Signoff
- High Capacity Approach Reduces Hardware Costs
- Complete Solution Ensures Comprehensive Signoff
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HyperScale
PrimeTime HyperScale technology extends PrimeTime static timing analysis to support designs beyond 500 million instances. It delivers between 5 and 10X better runtimes for the full chip timing analysis and 5 to 10X smaller memory footprint compared with classic flat analysis.
Advanced OCV
An accepted trend in the semiconductor industry, where process geometry is continuously shrinking, is the growing impact of variation in static timing analysis (STA). As on-chip-variation (OCV) effects continue to increase with shrinking geometry nodes, applying a flat global margin across the entire chip can lead to overdesign, reduced design performance, and longer timing closure cycles. The PrimeTime advanced OCV solution is a sophisticated technology that takes advantage of improved device-level variation modeling technique to provide the right balance between accuracy and performance.
What is the PrimeTime Special Interest Group (SIG)?
The Synopsys PrimeTime Special Interest Group (SIG) is an active community for all PrimeTime users and design engineers who want to stay connected with the latest developments in the field of Static Timing Analysis (STA). Increasing design size and complexity are putting tremendous pressure on design schedules. STA is a key technology used throughout the design process to accelerate design closure. As STA technology rapidly evolves, the PrimeTime SIG helps design teams stay abreast of the latest developments to help maximize their effectiveness and throughput.
PrimeTime SIG 2013 Events
PrimeTime SIG at SNUG India 2013
Advanced ECO Methodology
June 12, 2013 Dinner
PrimeTime SIG at DAC 2013
Technology Panel: Advanced ECO Methodology
June 3, 2013, Dinner and Music
PrimeTime SIG at SNUG Silicon Valley
Topic: PrimeTime ADV - Advanced Timing Technology
March 26, 2013 Dinner
PrimeTime SIG 2012 Events
PrimeTime SIG at SNUG Japan
Topic: Simultaneous Multi-voltage Timing Analysis
July 12, 2012, Luncheon
PrimeTime SIG at SNUG India
Topic: Next-generation Hierarchical Timing Technology - Hyperscale
June 13, 2012, Dinner
PrimeTime SIG at DAC 2012
Topic: Next-generation Hierarchical Timing Technology - HyperScale
June 4, 2012, Dinner
PrimeTime SIG at DATE 2012
Topic: Gigascale Design Signoff with Advanced OCV, ECO Guidance and HyperScale
13, March 2012, Luncheon
Archive
PrimeTime 2013 Webinar Series
On-Demand
Reducing Multi-mode STA Turnaround Time with PrimeTime Mode Merging - LSI Case Study
This webinar will introduce new PrimeTime technology to help design teams manage scenario increases by merging modes. LSI will discuss how PrimeTime mode merging allows them to reduce timing analysis.
Recover Leakage and Maintain Signoff Timing – with Customer Case Studies
This webinar will introduce PrimeTime ECO technology designed to recover leakage power, without introducing timing violations. We’ll share customer data that shows leakage power recovery up to 40%.
利用PrimeTime ECO Leakage Recovery 收复漏电功耗并保持签核时序-客户实例分析 – Simplified Mandarin
本次研讨会将介绍PrimeTime ECO leakage recovery 收复漏电功耗, 并保持签核时序的科技. 我们将分享客户设计的应用结果, 包括来自三星(Samsung)和法商ST(STMicroelectronics)的用户回馈, 显示使用IC Compiler和PrimeTime能收复高达40%的总漏电功耗.
利用PrimeTime ECO Leakage Recovery 收復漏電功耗並保持簽核時序 - 客戶實例分析 – Traditional Mandarin
本次研討會將介紹PrimeTime ECO leakage recovery 收復漏電功耗, 並保持簽核時序的科技. 我們將分享客戶設計的應用結果, 包括來自三星(Samsung)和法商ST (STMicroelectronics) 的用戶回饋, 顯示使用IC Compiler和PrimeTime能收復高達40%的總漏電功耗.
PrimeTime 2012 Webinar Series
On-Demand
利用PrimeTime Advanced OCV减少设计馀量 - Simplified Mandarin
学习芯片设计工程师如何利用PrimeTime Advanced OCV消除过度悲观的违例并加速设计收敛, 以及晶圆代工厂对这些新科技的看法和支持模式.
利用PrimeTime Advanced OCV減少設計餘量- Traditional Mandarin
學習晶片設計工程師如何利用PrimeTime Advanced OCV 消除過度悲觀的Violation以加速設計收斂, 以及晶圓代工廠對這些新科技的看法和支援模式.
Accurate Early Stage Power Estimation with PrimeTime PX: The NVIDIA Experience
In this webinar we will review the need for early power analysis, and show how useful power estimates can be achieved even with early and/or incomplete data. NVIDIA will outline their strategies.
网上活动: 利用PrimeTime节省数周ECO修复的时间
研讨芯片研发设计团队如何在综合与验收阶段节省数周的时间. 学习如何利用PrimeTime新世代的ECO导引功能自动化修复DRC, 建立时间, 与保持时间的违例, 进而缩减设计流程的迭代并缩短ECO修复所须的时间.
網上活動: 利用PrimeTime節省數週ECO的時間
研討晶片研發設計團隊如何在Implementation與Sign-off階段節省數週的時間. 學習如何利用PrimeTime新世代的ECO導引功能自動化修復DRC, Setup, 與Hold Violation, 進而縮減設計流程的Iteration並縮短ECO Fixing所須的時間.
5X Faster PrimeTime Multivoltage Timing Signoff: A Renesas Case Study
Learn how PrimeTime’s new multivoltage aware analysis technology reduces risk and speeds signoff for designs with multiple voltage domains, and how Renesas has successfully deployed it to reduce signoff turnaround time by 5X.
Faster PrimeTime Signoff - Tips, Tricks and New Technology
Learn how to achieve a 2X reduction in signoff TAT, and build the expertise to create high-performance signoff scripts.
Streamlining Your ECO Flow For Fastest Setup, Hold and Timing DRC Closure
Learn what’s new with timing-aware DRC guidance for ECOs and which design flow and tool settings provide the fastest timing closure at 28 nm and below.
PrimeTime 2011 Webinar Series
On-Demand
Faster Clock Analysis and Debug
Analyze clock constraints sooner, identify problems quicker, and debug timing violations faster. Learn how to save time using Galaxy Constraint Analyzer and PrimeTime to ensure clean clock constraints and keep clocks free of timing violations during signoff.
Save Weeks Fixing ECOs with PrimeTime and IC Compiler
See how design teams are saving weeks during implementation and signoff. Learn how PrimeTime Next-Generation ECO guidance and IC Compiler automatically fix DRC, setup and hold violations to reduce it.
Fast Timing Constraint Cleanup with Galaxy Constraint Analyzer
This technical webinar will explain how Galaxy Constraint Analyzer helps to produce signoff-quality timing constraints quickly, for even the most complex designs.
Debug Timing Faster with PrimeTime Visualization Tools
Save time debugging complex timing paths during implementation and signoff using new visualization techniques in PrimeTime. See new clock and data analysis capabilities in action.
Reducing Design Margins Using PrimeTime Advanced OCV - TSMC and User Views
Learn how designers are using PrimeTime Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about TSMC's views and support model for these new technologies.
PrimeTime 2010 Webinar Series
On-Demand
Performing Accurate Power Analysis on Low Power Designs Using PrimeTime PX
Learn how to analyze the effectiveness of low power techniques in your design, which modes of operation consume the most power, and how to deploy PrimeTime PX to optimize your design to meet low power requirements.
Faster ECO Fixing Flows with PrimeTime and IC Compiler
Learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively using Distributed Multi-Scenario Analysis for automatic set-up, hold and DRC fixing.
Reducing Design Margins Using PrimeTime Advanced OCV
Explains how Advanced On-Chip-Variation works in comparison to flat-derate OCV and statistical STA-based signoff technologies, and will contrast the cost of adoption and accuracy of these three methods.
Addressing Signal Integrity Noise in Low Power Design
Discusses the impact of low power design and the resulting requirements that drive the technologies in today's static timing analysis tools.