PrimeTime HyperScale Technology 

PrimeTime Scales Timing Analysis Beyond 500 Million Instances

HyperScale technology works with existing features like SI analysis, Advanced OCV for variation, and threaded multicore analysis to enable design teams increase their STA productivity and overall chip timing closure turn-around-time. HyperScale technology fits with today’s physical implementation flows where designs are implemented in blocks and then assembled into the chip level for final timing closure and signoff.

Press Releases

• PrimeTime 2010 Scales Timing Analysis Beyond 500 Million Instances

PrimeTime HyperScale SIG event

• PrimeTime SIG at DAC 2012
• Customer presentations are available for download from SolvNet
• PrimeTime SIG at SNUG Japan 2011
• Customer presentations are available for download from SolvNet.
• PrimeTime SIG 2010 – Silicon Valley
• Customer presentations are available for download from SolvNet.

Articles

• 20nm timing analysis – a practical and scalable approach
• Reducing Turnaround Time with Hierarchical Timing Analysis