SiliconSmart

Overview
SiliconSmart® is a comprehensive characterization solution for standard cells, I/O, complex cells and memory. It generates accurate model libraries tightly correlated with Synopsys' digital implementation tools. Its built-in FineSim™ simulation technology and tight integration with the gold-standard HSPICE® circuit simulator enable fast and accurate characterization across multiple process, voltage and temperature corners.

SiliconSmart Datasheet

Introduction
Accurate library characterization is the cornerstone of successful digital implementation. Synthesis, place-and-route, verification and signoff tools rely on detailed model libraries to accurately represent the timing, noise and power performance of digital and memory designs. The complexity of these libraries dramatically increases as designs migrate to lower process nodes, on which process variability calls for fast characterization on multiple corners – a process that repeats with every new device model version from the foundry. Low-power SoC design further complicates this process by introducing complex cells such as multivoltage level shifters and retention logic, which must be accurately characterized to ensure effective digital implementation across multiple power domains.

Figure 1: SiliconSmart, a single solution to characterize standard cells, complex cells, I/O and memory

SiliconSmart eliminates the library characterization bottleneck by generating accurate model libraries correlated with Synopsys' digital implementation tools. Its built-in FineSim simulation technology and tight integration with HSPICE enable fast and accurate characterization across multiple process corners, significantly reducing the time required to generate libraries in advanced nodes. SiliconSmart is easy to use, employing advanced function recognition and vector generation technology to automatically characterize complex cells, retention logic, and multi-voltage power management kits.

Fast Characterization Across Multi-CPU, Multi-Machine Systems
SiliconSmart delivers unparalleled characterization speed with its built-in FineSim SPICE simulator and tight integration with HSPICE. SiliconSmart intelligently combines measurements into simulation arcs, optimizing the number of simulations and accelerating that process through parallel characterization. Its adaptive parallel job manager distributes simulations to a network of computer servers and automatically adjusts CPU loading based on CPU performance and the job queuing platform. Overall characterization throughput improvements are nearly linear with each additional CPU. The default configuration for SiliconSmart supports five CPUs, but the user can increase this count to as many CPUs and simulator licenses as are available.

Automatic Function Recognition and Vector Generation
SiliconSmart reads in a CMOS transistor-level cell netlist and performs static structural analysis to automatically determine functionality. Based on Channel Connected Block (CCB) partitioning and logic cone tracing between primary outputs and inputs, this analysis handles a wide range of cells, from simple standard cells to very complex custom, macro or I/O cells. Circuit topology revealed by the automatic function recognition also allows SiliconSmart to generate a smart set of vectors to simulate all arcs inside a cell. This automatically generated vector set covers all necessary stimuli without any redundancy and minimizes the number of simulations required to characterize a cell without any loss of arc coverage or model accuracy. To enable characterization of only certain cell paths, SiliconSmart also supports the use of traditional user-defined functions and vector sets to guide the simulation sequence and measurement types for model creation.

Automatic function recognition and vector generation remove the dependency on a predefined function, such as that in an existing .lib file. This automation, combined with a rich set of supported features such as differential signals and variable electrical modes in a programmable cell, provide flexibility and ease-of-use in setting up a successful characterization run.

Pre-characterization and Constraint Acceleration Technology
SiliconSmart can further analyze the automatically generated vector set before final simulation. This precharacterization procedure includes sharing state-specific characterization conditions (also known as vector binning) and calling the built-in simulator to quickly grade these vectors in the bin. Controllable by a userdefined error-tolerance level, the whole set of vectors can be categorized into different bins. Only one simulation is required for a single bin. Other vectors in the same bin can be represented by the same measurement results in the created models.

SiliconSmart supports a wide range of constraint methodologies, from standard design flows to leading-edge performance applications for maximizing yield and performance. For example, SiliconSmart allows sampling of internal nodes in a sequential cell to look for glitches in order to remove potential optimism for setup/hold constraints. It also provides multiple ways of capturing the dependency between setup and hold checks for different design styles. The SiliconSmart constraint acceleration technology shortens the traditionally time-consuming task of measuring constraints.

Signoff and DFM Extensions
The SiliconSmart Signoff extension enables advanced modeling constructs that support the timing, power and noise analysis and repair flows that are required at advanced nodes. This includes support for the latest modeling formats such as CCS and ECSM for timing, power, and noise. The SiliconSmart DFM extension also generates statistical and process sensitivity information in variationaware models for timing and leakage. Design for manufacturability (DFM) characterization identifies cells prone to performance degradation due to lithographic (systematic) or process (random) variation, enabling optimization for better yields at higher frequencies.

Embedded Memory Recharacterization
A memory instance is generated by a memory compiler, which includes design netlist, physical layout, and electrical models. A memory compiler builds up its own database for modeling by simulating a very limited number of memory instances—usually a smallest, a largest and a few sizes in the middle.

For a newly created instance that is not on this short list of samples, the memory compiler uses interpolation and extrapolation to fit certain polynomial equations. It is inevitable that this approximation leads to inaccuracies in its models. SiliconSmart eliminate such inaccuracies by recharacterizing such instances accurately and quickly.

The SiliconSmart Memory solution delivers: Accurate memory instance recharacterization using a 100% simulation-based approach High throughput and capacity using the built-in FineSim Pro distributed simulation technology Effective stimulus-based netlist reduction to dynamically eliminate inactive portions of the memory netlist and speed up the simulation without compromising accuracy Ease of setup using internal node identification and templates for memory function description Recharacterization flexibility through simple vector generation and customization

Memory recharacterization applications: Embedded SRAM Synchronous/asynchronous Single-port/dual-port Embedded REG files Single-port/dual-port Embedded ROM

Comprehensive Library Validation
SiliconSmart includes a closed-loop library validation feature that compares cell functionality and data accuracy against a precharacterized golden library, ensuring model consistency between Liberty and Verilog formats. A library characterization run involves a large amount of data generation, collection and management.
SiliconSmart's data-dependency manager monitors file dependency in each characterization step and eliminates the need to recharacterize an entire library or any cell by immediately identifying which cells are affected by changes to the cell transistor netlist, SPICE model, or configuration settings. This ensures library consistency while significantly saving run time.

Silicon Smart Technology Features Built-in FineSim SPICE simulator and tight integration with HSPICE Parallel characterization distributed on heterogeneous compute farms with unlimited CPU counts Supports industry-standard load sharing systems LSF SUNGRID Automatic library characterization setup Automatic function recognition from SPICE netlist including state tablebased functions Automatic circuit topology-driven vector generation Automatic structure and/or simulation-based vector optimization (pre-char) Automatic constraint acceleration technology for sequential measurements Automatic characterization points and range selection Automatic gathering of all data from simulation to create all model views concurrently Active driver or emulated driver to supply realistic, non-linear input waveform shapes to characterization State- and path-dependent timing and power Dependency management via simulation caching Automatically recharacterization flow using an existing .lib file Tcl command line user interface

Cell Types Single- and multi-output combinatorial cells Complex latches and flip-flops, including retention flops, multi-bit flops, dual-edge flops Complex multi-voltage, bidirectional I/O cells Tri-state and open-drain cells Special cells including one-hot MUX, bus keeper and clock gating Special I/O cells such as LVDS, USB, PGIO, DDR, PCI, SSTL

Inputs SPICE transistor-level netlists Differential inputs and outputs Multiple voltage supplies User-specifiable complex load networks Characterization of multiple electric modes per driver

Outputs Liberty (.lib) Non-linear delay model (NLDM) Non-linear power model (NLPM) CCS timing, power, noise, variationaware Compact CCS ECSM (version 2.1.1) timing, power, statistical (S-ECSM) Verilog VHDL/Vital IBIS 5.0 I/O models

Figure 2: SiliconSmart inputs and outputs

Measurements Intrinsic delay and output transition time Effective input pin capacitance Minimum pulse widths Setup, hold, recovery and removal times Constraint edge control Dependent or independent setup and hold Constraint violation determination Functional failure Absolute, relative and user-defined delay or slew degradation Output and internal node glitch checking Leakage and internal (transition and hidden) power Statistical model measurements IBIS 5.0 measurements Current and voltage curves plus different launch delay On-die termination (ODT) Programmable driver strength Optimal point selection for static IV curve generation

Validation Features Liberty model comparison Automatic Verilog/Vital functional and back-annotation validation

Supported SPICE Simulators HSPICE FineSim Cadence Spectre Mentor Graphics Eldo

Platform Support Red Hat Linux SUSE Linux Load Sharing Systems: LSF, SUNGRID