Galaxy Signoff 

Accelerate Innovation with Design Analysis and Signoff 

Unleashing the performance potential of advanced silicon process technology without the risk of design failure is one of the single biggest design closure challenges facing designers. Synopsys brings a broad integrated portfolio of state-of-the art design analysis and signoff technology all based on the golden signoff foundation customers have come to trust. The Galaxy signoff solutions deliver all the ingredients necessary from library generation with composite current source (CCS) modeling to statistical timing analysis, advanced signal integrity and IR-drop based analysis and signoff. Combining Galaxy signoff with IC Compiler™ and IC Compiler II physical implementation solutions' tight correlation and ECO integration allows designers to confidently unleash the full performance potential with the fastest design closure.

  • PrimeTime
  • Golden timing signoff including STA, SI, Power and timing constraint analysismore

  • NanoTime
  • Transistor-level STA for Custom Designs and Embedded Memoriesmore

  • PrimeRail
  • In-Design Rail Analysis for Place-and-Route Engineers more

  • StarRC
  • Industry leading parasitic extraction for digital and custom designmore

  • QuickCap NX
  • 3D field solver for 14nm FinFET and beyond process technologiesmore

A comprehensive characterization solution for standard cells, I/O complex cells and memory.

Key Benefits
  • Golden accuracy to ensure silicon success through trusted timing and extraction foundation
  • Sign-off in any digital implementation flow through standard library and data format support
  • Comprehensive full-chip sign-off through integrated gate-level and transistor-level support
  • Fastest turnaround time through integrated easy-to-use environment, high capacity and fast runtime performance, and the most efficient multi-core compute farm support
  • Fastest time to design closure with the highly correlated and tightly integrated Galaxy Design Platform

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