Webinars 

Samsung Saves 20% Total Power on FinFET Designs with PrimeTime Signoff-driven ECO - Simplified Chinese
Join Synopsys as they discuss physically-aware ECO power recovery for advanced designs. Learn how Samsung reduced total power by 20% using PrimeTime ECO’s latest power recovery technology.
James Chuang, Technical Marketing Manager, Synopsys
Oct 22, 2014
 
Samsung Saves 20% Total Power on FinFET Designs with PrimeTime Signoff-driven ECO - Traditional Chinese
Join Synopsys as they discuss physically-aware ECO power recovery for advanced designs. Learn how Samsung reduced total power by 20% using PrimeTime ECO’s latest power recovery technology.
James Chuang, Technical Marketing Manager, Synopsys
Oct 22, 2014
 
Samsung Saves 20% Total Power on FinFET Designs with PrimeTime Signoff-driven ECO
Join Synopsys as they discuss physically-aware ECO power recovery for advanced designs. Learn how Samsung reduced total power by 20% using PrimeTime ECO's latest power recovery technology.
Vivek Ghante, Senior Corporate Applications Engineer, Synopsys; James Chuang, Technical Marketing Manager, Synopsys
Oct 01, 2014
 
Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow - Simplified Chinese
Simplified Chinese: Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Chung Yang, CAE, Synopsys
May 28, 2014
 
Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow - Traditional Chinese
Traditional Chinese: Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Chung Yang, CAE, Synopsys
May 28, 2014
 
Accurate and Faster Timing Closure with TSMC 16-nm FinFET using Synopsys-certified Signoff Flow
Join TSMC and Synopsys as they discuss advanced modeling at the FinFET 16-nm technology node and its impact to extraction and timing analysis.
Chiming Li, Technical Manager, TSMC; Carol Scemanenco, Senior Staff Engineer, Synopsys
May 27, 2014
 
Latest Advances in PrimeRail In-Design Vector Free Rail Analysis
See the latest innovations in PrimeRail's In-Design solution including rail integrity and static/dynamic analysis that enable designers to achieve significant productivity in advanced node designs.
Jason Binney, Principle CAE, Synopsys
May 14, 2014
 
Counting Down to 10 nm: GLOBALFOUNDRIES and Synopsys Perspective on Future Extraction
GLOBALFOUNDRIES and Synopsys will discuss the implications for extraction as foundries move to the next level of die shrink at 10nm.
Jongwook Kye, Fellow, GLOBALFOUNDRIES; Beifang Qiu, Senior R&D Manager, Synopsys
Apr 30, 2014
 
Fastest Multi-scenario Timing Closure with PrimeTime Physically-aware ECO - AMD Shares Results (Simplified Chinese)
AMD and Synopsys will discuss the latest enhancements to PrimeTime's ECO Guidance technology to accelerate multi-scenario timing closure.
James Wai, Director of Physical Design, AMD; Chung Yang, Staff CAE, Synopsys
Dec 19, 2013
 
Fastest Multi-scenario Timing Closure with PrimeTime Physically-aware ECO - AMD Shares Results (Traditional Chinese)
AMD and Synopsys will discuss the latest enhancements to PrimeTime's ECO Guidance technology to accelerate multi-scenario timing closure.
James Wai, Director of Physical Design, AMD; Chung Yang, Staff CAE, Synopsys
Dec 19, 2013
 
Fastest Multi-scenario Timing Closure with PrimeTime Physically-aware ECO - AMD Shares Results
AMD and Synopsys will discuss the latest enhancements to PrimeTime’s ECO Guidance technology to accelerate multi-scenario timing closure.
Rajit Seahra, Senior Fellow, AMD; Vivek Ghante, Senior Corporate Applications Engineer, Synopsys
Oct 31, 2013
 
GLOBALFOUNDRIES and Synopsys Share Signoff Best Practices for 20/14-nm - Simplified Mandarin
This webinar will outline the essential elements of an effective advanced node signoff flow with PrimeTime and StarRC.
Adrian Au-Yeung, Member of Technical Staff, GLOBALFOUDARIES; James Chuang, Technical Marketing Manager, Synopsys
Oct 29, 2013
 
GLOBALFOUNDRIES and Synopsys share signoff best practices for 20/14-nm - Traditional Mandarin
This webinar will outline the essential elements of an effective advanced node signoff flow with PrimeTime and StarRC.
Adrian Au-Yeung, Member of Technical Staff, GLOBALFOUDARIES; James Chuang, Technical Marketing Manager, Synopsys
Oct 29, 2013
 
GLOBALFOUNDRIES and Synopsys Share Signoff Best Practices for 20/14-nm Design
This webinar will outline the essential elements of an effective advanced node signoff flow with PrimeTime and StarRC.
Dr. Tamer Ragheb, SMTS CAD Engineer, GLOBALFOUNDRIES; Dr. Ayhan Mutlu, Sr. Manager, Corporate Applications Engineer, Synopsys
Jul 31, 2013
 
Reducing Multi-mode STA Turnaround Time with PrimeTime Mode Merging - LSI Case Study
This webinar will introduce new PrimeTime technology to help design teams manage scenario increases by merging modes. LSI will discuss how PrimeTime mode merging allows them to reduce timing analysis.
Harish Aepala, Principal Methodology Engineer, LSI; Srinivas Muddagowni, Corporate Applications Engineer, Synopsys
Mar 27, 2013
 
Recover Leakage and Maintain Signoff Timing – with Customer Case Studies
This webinar will introduce PrimeTime ECO technology designed to recover leakage power, without introducing timing violations. We’ll share customer data that shows leakage power recovery up to 40%.
Rupesh Nayak, R&D Manager, Synopsys; Sasan Absalan, Corporate Applications Engineer, Synopsys
Jan 29, 2013
 
Reducing Design Margins Using PrimeTime Advanced OCV - Simplified Mandarin
Learn how designers are using Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about customer and foundries’ deployment and support model for this technology.
James Chuang, Technical Marketing Manager, Implementation Group, Synopsys
Dec 12, 2012
 
Reducing Design Margins Using PrimeTime Advanced OCV - Traditional Mandarin
Learn how designers are using Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about customer and foundries’ deployment and support model for this technology.
James Chuang, Technical Marketing Manager, Implementation Group, Synopsys
Dec 12, 2012
 
Double Patterning Ready Extraction and Signoff: TSMC and Synopsys Update
Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.
Anderson Chiu, Technical Manager, TSMC; Beifang Qiu, Senior R&D Manager, Synopsys
Dec 05, 2012
 
Double Patterning Ready Extraction and Signoff: TSMC - Simplified Mandarin
Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.
Anderson Chiu, Techincal Manager, TSMC; Beifang Qiu, Senior R&D Manager, Synopsys
Dec 05, 2012
 
Double Patterning Ready Extraction and Signoff: TSMC and Synopsys Update - Traditional Mandarin
Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.
Beifang Qiu, Technical Manager, Synopsys; Anderson Chiu, Senior R&D Manager, TSMC
Dec 05, 2012
 
Accurate Early Stage Power Estimation with PrimeTime PX: The NVIDIA Experience
In this webinar we will review the need for early power analysis, and show how useful power estimates can be achieved even with early and/or incomplete data. NVIDIA will outline their strategies.
Miodrag Vujkovic, Senior ASIC Design Engineer, NVIDIA; Maria Tovey, Corporate Applications Engineer, Synopsys
Oct 04, 2012
 
FinFET Process Modeling and Extraction at 16-nm and Below
Synopsys' R&D will discuss the motivation behind FinFETs and describe how Synopsys is driving the collaboration with major foundries to develop a next-generation extraction solution.
Bari Biswas, Senior Director R&D, Synopsys
Sep 27, 2012
 
Save Weeks Fixing ECOs with PrimeTime (Simplified Mandarin)
Learn how PrimeTime Next-Generation ECO guidance automatically fix DRC, setup and hold violations to reduce iterations and shorten ECO fixing turn-around time.
James Chuang, Synopsys
Sep 26, 2012
 
Save Weeks Fixing ECOs with PrimeTime (Traditional Mandarin)
Learn how PrimeTime Next-Generation ECO guidance automatically fix DRC, setup and hold violations to reduce iterations and shorten ECO fixing turn-around time
James Chuang, Synopsys
Sep 26, 2012
 
5X Faster PrimeTime Multivoltage Timing Signoff: A Renesas Case Study
Learn how PrimeTime’s new multivoltage aware analysis technology reduces risk and speeds signoff for designs with multiple voltage domains, and how Renesas has successfully deployed it to reduce signoff turnaround time by 5X.
Francis Cheung, Senior Staff Engineer, EDA Engineering, Engineering Unit , Renesas Electronics America, Inc.; Carol Scemanenco, Senior Staff Engineer, Implementation R&D Group, Synopsys, Inc.
Jul 31, 2012
 
Faster PrimeTime Signoff - Tips, Tricks and New Technology
Learn how to achieve a 2X reduction in signoff TAT, and build the expertise to create high-performance signoff scripts.
Tzong-Maw Tsai, CAE Director, Synopsys; Amrita Sahoo, Senior Corporate Applications Engineer, Synopsys
Apr 25, 2012
 
Streamlining Your ECO Flow For Fastest Setup, Hold and Timing DRC Closure
Learn what’s new with timing-aware DRC guidance for ECOs and which design flow and tool settings provide the fastest timing closure at 28 nm and below.
Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys; Vivek Ghante, Staff Corporate Applications Engineer, Implementation Group, Synopsys
Mar 14, 2012
 
Faster Clock Analysis and Debug
Learn how to save time using Galaxy Constraint Analyzer and PrimeTime to ensure clean clock constraints and keep clocks free of timing violations during signoff.
Karen Linser, Staff Corporate Applications Engineer, Implementation Group, Synopsys; Robert Landy, Staff Corporate Applications Engineer, Implementation Group, Synopsys
Oct 25, 2011
 
Save Weeks Fixing ECOs with PrimeTime and IC Compiler
See how design teams are saving weeks during implementation and signoff. Learn how PrimeTime Next-Generation ECO guidance and IC Compiler automatically fix DRC, setup and hold violations to reduce it.
Troy Epperly, Staff Engineer, CAE, Implementation Group, Synopsys; Tzong-Maw Tsai, Director, CAE, Implementation Group, Synopsys
Jul 20, 2011
 
Fast Timing Constraint Cleanup with Galaxy Constraint Analyzer
Learn how Galaxy Constraint Analyzer helps to produce signoff-quality timing constraints quickly, for even the most complex designs. Hear how AMD uses Galaxy Constraint Analyzer for quality assurance.
Richard Bishop, Member of Technical Staff, AMD; Karen Linser, Senor Corporate Applications Engineer, Implementation Group, Synopsys
May 18, 2011
 
Debug Timing Faster with PrimeTime Visualization Tools
Save time debugging complex timing paths during implementation and signoff using new visualization techniques in PrimeTime. See new clock and data analysis capabilities in action.
Robert Landy, Staff Corporate Applications Engineer, Implementation Group, Synopsys; Philip Cuney, Design Support Technical Leader, Design Support & Methodology Group, Home Entertainment & Displays, ST Microelectronics
Apr 20, 2011
 
Reducing Design Margins Using PrimeTime Advanced OCV – TSMC and User Views
Learn how designers are using PrimeTime Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about TSMC’s views and support model for these new technologies.
Willy Chen, Program Manager, Design Methodology Division, TSMC; Norb Heindl, Senior Staff Engineer CAE, Implementation Group, Synopsys
Feb 23, 2011
 
Faster ECO Fixing Flows with PrimeTime and IC Compiler
This technical webinar will explain how IC Compiler and PrimeTime can be used to close timing during signoff. It will focus on the use of Distributed Multi-Scenario Analysis for automatic set-up and hold fixing, and will explain new PrimeTime 2010.06 DRC fixing capabilities. Attendees will learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively.
Uyen Tran, Director, CAE, Implementation Group, Synopsys; Jennifer Pyon, Senior Staff Engineer, CAE, Implementation Group, Synopsys
Jul 20, 2010
 
Reducing Design Margins Using PrimeTime Advanced OCV
How Advanced On-Chip-Variation works in comparison to flat-derate OCV and SSTA-based signoff technologies. Techniques for deploying PrimeTime to reduce pessimistic endpoints and slack pessimism.
Uyen Tran, Director CAE, Synopsys; Norb Heindl, Senior Staff Engineer, CAE, Synopsys
Feb 17, 2010
 
Addressing Signal Integrity Noise in Low Power Design
A discussion on the impact of low power design and the resulting requirements that drive the technologies in today’s static timing analysis tools. Learn about PrimeTime SI techniques that will enable you to deploy the SI noise-aware flow that best fits your needs for fast, accurate signoff.
Tzong-Maw Tsai, Director, Corporate Applications Engineer, Synopsys; Troy Epperly, Corporate Applications Engineer, Synopsys
Jan 20, 2010
 


NewsArticlesWhite PapersWebinars