With process geometries reaching 28-nanometers (nm) and below, there are many nanometer effects that can impact timing. Accurate analysis of these effects is required to identify real timing issues.
Synopsys’ NanoTime tool is an advanced transistor-level static timing analysis solution that addresses the emerging challenges in signal integrity (SI) analysis associated with custom designs and embedded memories.
NanoTime offers concurrent timing and SI analysis, accuracy within plus-minus five percent of HSPICE®, and has the performance required to analyze complex transistor circuits and embedded memories overnight. Its seamless integration with Synopsys’ PrimeTime® product enables full-chip analysis of designs that includes both gate- and transistor-level blocks. NanoTime is a key component of the Synopsys custom design verification solution that includes CustomSim® and HSPICE for circuit simulation and ESP-CV for symbolic simulation.
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STA-Based Memory Characterization
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Accurate transistor-level analysis of crosstalk- delay and noise
As designs go down to 28-nm and below, crosstalk-delay comprises the majority of the total delay. Prior solutions including traditional static timing analysis with optional 3rd party crosstalk delay and noise analysis do not provide the accuracy and productivity that is required. Concurrent timing and SI crosstalk-delay and noise analysis is a must to achieve silicon success.
Accurate static timing analysis and model generation of embedded memories
As memory content in System-on-Chip (SoC) continues to increase, more and more silicon area will consist of memories with different functionality in the forms of embedded SRAM, ROM, and multi-port register files. The complexity of designs and verification challenges with embedded memories steadily increase with shrinking geometry. A new methodology with model generation capability to improve the overall engineering turn-around time is essential to meet today’s time-to-market requirements.
Full chip timing verification
Transistor- and gate-level static timing analysis need to work together to deliver full chip timing verification. A seamless and accurate timing analysis flow from custom design to gate-level with PrimeTime achieves this. To enable higher productivity, NanoTime has the same commands as PrimeTime whenever they are applicable. Figure (1) illustrates a simplified full-chip static timing signoff flow.
Figure 1. Full-Chip Static Timing Signoff Flow
NanoTime offers higher predictability and improved productivity to custom designers over traditional solutions. Its concurrent timing and SI features enable designers to accurately and quickly identify timing issues early and avoid expensive silicon re-spins. NanoTime helps ensure silicon-accurate analysis and delivers overnight analysis results for complex million-transistor designs. NanoTime further boosts designer productivity by offering significant ease-of-use features, including interactive static timing analysis, extracted timing model (ETM) creation, and seamless integration with PrimeTime. In addition, Synopsys also offers a suite of custom design verification tools that operate within the Custom Designer Environment as shown in figure (2) and figure (3).
Figure 2. Synopsys Custom Design Verification Suites
Figure 3. NanoTime and Custom Designer Integration
- Key Features and Benefits of NanoTime
- Timing analysis and model generation for custom macros and embedded memories
- Vectorless and exhaustive full timing paths coverage
- Accuracy within ±5% of HSPICE
- Improved productivity with Custom Designer integration
- Seamless integration with PrimeTime for full-chip static timing analysis signoff
- Built-in RC reduction
- Extensive device model support including custom model interface
Figure 4. NanoTime Overview and Key Features
- NanoTime for Embedded Memories (as shown in Figure 5)
Synopsys’ breakthrough memory feature addition to NanoTime enables designers to effectively analyze complex transistor circuits and embedded memories overnight.
- NanoTime includes a static timing analysis and memory characterization solution using a hybrid of static and dynamic circuit analysis techniques
- NanoTime's memory feature reads in a memory netlist and outputs timing reports and/or CCS/NLDM timing + noise models
Figure 5. NanoTime memory feature
- Additional Features of NanoTime
- Provide longest and shortest path reports, considering crosstalk impact
- Set up, hold and transparency timing checks for sequential circuits
- Timing checks for complex circuit designs (domino logic, pass gates, gated clocks)
- Slack analysis
- Intelligent false path suppression
- Post-layout analysis with RC back-annotation
- Direct advanced model support
- On-demand dynamic simulation capability for complex data and clock structures
- Multiple voltage support
- Transparent Extracted Timing Model generation that natively works with PrimeTime
- Ability to merge timing models
- Industry-standard support, Liberty™, SDC, SPF, SPEF