| Experts At The Table: The Growing Signoff Headache |
Low-Power/High-Performance Engineering sat down to discuss signoff issues with Robert Hoogenstryd, senior director of marketing for signoff at Synopsys, and more.
May 09, 2013 |
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| 20nm timing analysis – a practical and scalable approach |
Using hierarchy and improved constraints management to accelerate static timing analysis at 20nm and below.
Dec 06, 2012 |
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| Reducing Turnaround Time with Hierarchical Timing Analysis |
PrimeTime HyperScale technology addresses the existing challenges of STA on hierarchical designs and enables seamless hierarchical STA signoff on multi-million instance SoCs like those used in today's smart phones.
Oct 03, 2011 |
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| Synopsys introduced PrimeTime’s next generation ECO technology |
The new technology targeted at the overall optimal ECO guidance, considers all the possible violations. This technology also reduces the runtime. Ikutaro Kojima, Tech-On!, Nikkei BP (The article is written in Japanese)
Jan 29, 2011 |
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| Expert Shootout: Parasitic Extraction |
Low-Power Engineering sat down to discuss parasitic extraction with Robert Hoogenstryd, director of marketing for design analysis and signoff at Synopsys
Feb 11, 2010 |
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| Static Timing Analyzer Goes Multicore And Distributed |
Synopsys continues to follow through on its multicore initiative, which the company announced in March 2008.
Jan 27, 2010 |
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| Threaded multicore processing ready for Synopsys' PrimeTime |
EDA and IP vendor Synopsys Inc. said it has added threaded multicore processing to its latest release of PrimeTime static analysis tool, enabling up to 2x speed of timing signoff.
Jan 11, 2010 |
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| How to multithread a timing analyzer |
http://www.edn.com/blog/1690000169/post/1260051926.html
Jan 11, 2010 |
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| PrimeTime 2009.12 Delivers New Threaded Multicore Performance |
Synopsys, Inc. announced the immediate availability of PrimeTime 2009.12, which it claims delivers up to 2X speed up of timing signoff through the addition of threaded multicore processing.
Jan 11, 2010 |
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| Synopsys expands parasitic extraction capabilities for AMS designs |
EDA and IP vendor, Synopsys Inc. has expanded its parasitic extraction tools with analog mixed-signal (AMS) and custom digital IC designers in mind.
Sep 28, 2009 |
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| Synopsys reorganizes extraction offerings: Star RC becomes trinary system |
Synopsys reorganizes extraction offerings: Star RC becomes trinary system
Sep 21, 2009 |
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| Synopsys offers StarRC Custom extraction tool |
Synopsys, Inc. has extended its Galaxy implementation platform with the StarRC Custom parasitic extraction solution for analog mixed-signal and custom digital IC design.
Sep 21, 2009 |
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| Flexible Analysis is Key to Power Integrity |
Find out why millions of business professionals turn to LexisNexis® to gain unique insights and make informed decisions.
Oct 20, 2008 |
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| Accellera Rolls Power Plan |
Welcome to EETimes, where engineers make their own connections. Meet your peers, discuss your work, find a mentor, talk tech, get advice, sound off, make some "inside" contacts, expand your career.
Oct 20, 2008 |
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| Statistical timing gets a foothold in leading-edge designs |
Is statistical timing analysis really helping anyone, or is it an EDA-industry marketing ploy? This simmering debate within the leading edge of the chip design community bubbled to the surface in the plenary sessions Wednesday during the International Symposium on Quality Electronic Design (ISQED). The topic was the subject of both a lunch-time panel discussion and a plenary paper by one of the founders of the sport, IBM's Chandu Visweswariah.
Mar 24, 2008 |
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| Industry Ready to Sign On to Statistical Timing Signoff |
Until recently, statistical static timing analysis (SSTA) had been the darling of EDA-centric technical conferences and symposia for several years.
Sep 27, 2007 |
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| Process Variations Require Integrated Sign-Off Solutions |
In the traditional ASIC design flow, the sign-off stage was a key, well-defined point in the chip-making process. The designers would complete their front-end design and gate-level implementation, run timing sign-off using a static timing analysis tool, and hand the design to the ASIC foundry along with the timing constraints.
Jul 06, 2007 |
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| Synopsys donates technology to Accellera low power effort |
Top-tier EDA vendor Synopsys Inc. said Tuesday (Sept. 19) it has donated power management technology to the Unified Power Format (UPF) standardization effort of EDA standards organization Accellera.
Sep 19, 2006 |
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| Power integrity analysis for billion-transistor full-custom designs |
While the move to advanced process technologies has enabled levels of integration to reach new heights, engineers must now work harder than ever to realize those benefits.
Sep 17, 2006 |
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| How Much Test Compression is Enough? |
Each new manufacturing process generation brings with it a whole new set of challenges. In an era of multimillion-gate complexity and increasing density of nanometer manufacturing defects, a key challenge today is creating the highest quality deep submicron (DSM) manufacturing tests in the most cost-effective manner possible.
Feb 20, 2006 |
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