Videos

		Design Compiler Customer Videos Industry experts from Samsung, Qualcomm, Cisco and Synopsys discuss how they are utilizing DC Explorer and Design Compiler Graphical to tackle the challenges of ever-increasing design complexities amidst shrinking schedules. Eyal Odiz, VP of Engineering, Synopsys, Cheal Rim, Sr. Engineer, Samsung, Troung Hoang Principal Engineer/Manager, Qualcomm, Venkataraman Srinivasagam,Technical Leader, Cisco

		DC Explorer Video Introducing DC Explorer Antun Domic, General Manager, Implementation Group, Synopsys, Inc.

		Accelerate Product Ramp with TetraMAX ATPG and Yield Explorer Girish Patankar discusses diagnostics in TetraMAX ATPG, accuracy improvements with physical diagnostics, and how TetraMAX ATPG and Yield Explorer form a complete solution for volume diagnostics. Girish Patankar, Sr. R&D Manager

		Galaxy Test 2010.03 Introduction Amy Mitby introduces the latest release and highlights four new powerful features Amy Mitby, Sr. Test Applications Consultant

		Small Delay Defects: The Need for Better At-Speed Tests Manufacturing process variations can introduce small delays that adversely affect critical design paths, leading to circuit failures. Dr. T.W. Williams introduces technology developed at Synopsys to detect defects creating these delays, thereby increasing the test quality. Tom Williams, Synopsys Fellow

		Perspective: Boost your design productivity Design Compiler Graphical, the newest member of the Design Compiler product family, creates a better starting point for physical implementation and can shave weeks off your design schedule. Antun Domic, senior vice president and general manager of Synopsys' Implementation Group

		Pin-Limited Test Current trends are accelerating the need for pin-limited test. Amy Mitby introduces capabilities in DFTMAX compression that allows designers to achieve predictable compression of up to 100X or more with only one pair of test data pins. Amy Mitby, Sr. Test Applications Consultant

		Power-Aware Test Conventional compression tools create patterns that force the device under test to consume up to ten times more power compared to normal operation, leading to IR drop and overheating. Tom Williams, Synopsys Fellow

		Perspective: How to Improve Design TTR John Chilton, senior vice president of Marketing and Business Development at Synopsys, talks about the importance of utilizing today’s widely-available multi-core processor-based compute infrastructures to accelerate design TTR. John Chilton, senior vice president of Marketing and Business Development at Synopsys