Synopsys at ITC 2013 

Higher Quality, Lower Cost. Faster. 
Synopsys 21st Annual Test SIG
Monday, September 9, 2013
6:30 p.m. – 9:30 p.m.
Disney's Grand Californian Hotel, Anaheim, CA
Sequoia Ballroom

Register Now!

Attend Synopsys’ exclusive Special Interest Group (SIG) event at ITC 2013 in Anaheim, California, hosted by industry luminary Tom Williams. Please join us for appetizers, beer and wine, followed by a sit-down dinner. Synopsys’ Rohit Kapur and Yervant Zorian will introduce innovative new technologies in the Synopsys synthesis-based test solution. Test experts from leading companies will then present how they are deploying these technologies to boost compression, significantly lower test costs and improve turnaround time implementing hierarchical test for large SoCs and IP. Speakers include:

  • Swapnil Bahl, STMicroelectronics
  • Charutosh Dixit, LSI
  • And others

After the presentations, be sure to join Synopsys’ R&D staff for coffee and dessert and discuss any of your test-related questions.

Prize drawing: All attendees will be entered in a raffle to win a Lytro light field camera.

Seating is limited, so please register early for this important event.

The Grand Californian is a 5-minute walk from Disneyland Hotel.
Map: Disneyland Hotel to Grand Californian Hotel

ITC 2013

Test Week: Sunday, September 8 to Friday, September 13
Conference and exhibition: Tuesday, September 10 to Thursday, September 12
Exhibit Hours:
Tuesday, September 10, 10:30 a.m. – 5:30 p.m.
Wednesday, September 11, 9:30 a.m. – 4:30 p.m.
Thursday, September 12, 9:30 a.m. – 1:00 p.m.

Synopsys Booth #111
Come and see the latest innovations in Synopsys' synthesis-based test solution for the fastest path to high-quality, low-cost silicon manufacturing test and yield analysis. The solution is comprised of DFTMAX™ and TetraMAX® ATPG for power-aware logic test and physical diagnostics, DesignWare® STAR Memory System® for test, repair and diagnostics of embedded memories, DesignWare IP for self-test of high-speed SERDES interfaces, Yield Explorer for design-centric yield analysis, and Camelot™ for CAD navigation. We'll demonstrate how you can use new capabilities to:

  • Lower test costs by an additional 20-30x
  • Improve turnaround time implementing hierarchical test for large SoCs and IP
  • Increase the accuracy of physical diagnostics
 Prize drawing Tuesday and Wednesday in the Synopsys booth!
Win a Lytro camera. Stop by the Synopsys booth (#111) to enter the raffle.

Synopsys Activities at ITC 2013
8:30 a.m. – 12:00 p.m.
TUTORIAL 8: Hierarchical Test: Trends, Challenges and Solutions
A. Cron, Y. Zorian, Synopsys (Presenters)

1:00 p.m. – 4:30 p.m.
TUTORIAL 13: Advanced Memory BIST and Repair in Nanometer and FinFET Era
Y. Zorian, Synopsys (Presenters)

6:30 p.m. – 9:30 p.m.
21st Annual Synopsys Test SIG Event

10:30 a.m. – 12:00 p.m.
Y. Zorian, Synopsys (Chair)

4:00 p.m. – 5:30 p.m.
SESSION 4: Scan Compression for Large Designs
4.1 Two-level Compression Through Selective Reseeding
P. Wohl, J. Waicukauski, F. Neuveux, G. Maston, N. Achouri, Synopsys; J. Colburn, NVIDIA

8:30 a.m.–10:00 a.m.
LECTURE 2: Advanced Measurement Techniques
G. Maston, Synopsys (Chair)

12:00 p.m. – 2:00 p.m.
Poster Session PO 4: Assertions in Library ATPG Models for Robust Scan Patterns
K. Abdel-Hafez, S. Talluto, Synopsys; S. Bahl. P.R. Gupta, H. Kaur, M. Jain, STMicroelectronics

2:00 p.m. – 4:00 p.m.
SESSION 10: Advances in Test Generation
10.4 A Distributed Multicore Hybrid ATPG System
X. Cai, P. Wohl, Synopsys

2:00 p.m. – 3:30 p.m.
PANEL 5: The Battle of the Standards
R. Kapur, Synopsys (Organizer)
A. Cron, Synopsys (Panelist)

4:30 p.m. - 7:00 p.m.
4th IEEE International Workshop on Testing Three-Dimensional Stacked ICs
Y. Zorian, Synopsys (General Chair)

FRIDAY, 9/13
8:00 a.m. - 4:00 p.m.
4th IEEE International Workshop on Testing Three-Dimensional Stacked ICs
Y. Zorian, Synopsys (General Chair)
A. Cron, Synopsys (Panelist)

For more information about Synopsys' synthesis-based test solution visit

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