Synthesis-Based Test 

Higher Quality, Lower Cost. Faster 

Ensuring that complex SoCs meet manufacturing test requirements is a significant challenge. The Synopsys synthesis-based test solution maximizes productivity, providing designers, DFT engineers and product engineers with the fastest and most cost-effective path to high-quality manufacturing tests and high-volume silicon. Synthesis-based technology minimizes the impact test logic has on design timing, area, power and congestion. This eliminates time-consuming iterations between RTL synthesis, test and physical implementation, helping designers converge on both test and design goals faster. The test solution is comprised of DFTMAX™ Ultra, DFTMAX and TetraMAX® for power-aware logic test and physical diagnostics; DesignWare® STAR Hierarchical System for IEEE standards-based hierarchical SoC test; DesignWare STAR Memory System® for embedded and external memory test, repair and diagnostics; DesignWare IP for high-speed interfaces with self-test; Yield Explorer for design-centric yield analysis; and Camelot™ for CAD navigation.

 






 
Complete Interface IP Solutions for the Most Popular Protocols


Logic Test and Diagnostics
  • Built into Design Compiler for faster time-to-results meeting timing, power, area, and test
  • High compression enables low test cost, high test quality for today’s complex designs
  • Compression utilizes as few as one scan channel for pin-limited test
  • Integrated logic and memory test for faster design closure, smaller area overhead
  • Advanced fault models for ultra-high test quality: slack-based transition delay, static/dynamic bridging, hold-time, internal cell, and FinFET testing
  • Links with PrimeTime® and StarRC™ for high defect-coverage testing
  • Power-aware testing to reduce power consumption during test and avoid yield loss
  • IEEE 1149.1 implementation and verification to meet boundary scan requirements
  • Hierarchical test for faster turnaround time of large SoCs and IP
  • Physical diagnostics and yield analysis for fast and accurate failure analysis
Memory Test, Repair and Diagnostics
  • Coverage for existing and new memory defects at 20 nm and below
  • Integrated logic and memory test for faster design closure, smaller area overhead
  • High-performance processor cores interface support maximizes SoC performance
  • Dynamic IP test scheduling for lower test time and power consumption
  • Integrated with hierarchical test for faster turnaround time of large SoCs and IP
IP Test
  • Self-test of DesignWare SERDES IP for fast debug of high-speed interfaces
  • Hierarchical integration of IPs for faster turnaround time
  • Dynamic IP test scheduling for lower test time and power consumption
  • Automated porting of IP-level patterns to the SoC level alleviates capacity bottlenecks
Design-Centric Yield Analysis
  • Design-centric yield analysis for determining the root cause of silicon defects
  • Direct interface between ATPG and yield analysis for high volume diagnostics throughput


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