 Test Automation of 3D Integrated Systems |
This whitepaper discusses some of the key challenges related to testing 3D integrated systems, and how early adopters can use Synopsys' synthesis-based test solution to maximize their productivity when implementing test for 3D systems.
Chris Allsup, Marketing Manager, Synopsys |
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| Synthesis-Based Test For Maximum RTL Designer Productivity |
Synopsys provides test technology embedded in synthesis, or “synthesis-based test”, to implement the key aspects of DFT for scan testing, boundary scan, embedded memory test, on-chip testing of high-speed blocks like USB and PCI Express® cores and connections to yield analysis.
Robert Ruiz, Product Marketing Manager,
Synopsys |
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| Testing Low Power Designs with Power Aware Test |
The most important trend over the past decade for semiconductor design is the dominant requirement to reduce power consumption and power dissipation. Not only do competitive products require more functionality and higher performance, they must fit into increasingly smaller and more portable products.
Cy Hay, Product Manager, Synopsys |
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| Using TetraMAX® Physical Diagnostics for Advanced Yield Analysis |
Scan-based DFT is now the standard digital logic testing used on almost all SoC designs.
Cy Hay, Product Manager |
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| Multicore and Distributed Processing With TetraMAX® ATPG |
Running automatic test pattern generation (ATPG) on a single processor may take a week or longer to complete, especially for very large designs and when testing at-speed fault models. Designers and test engineers need a straightforward way to reduce ATPG runtime by many factors and deliver working test patterns in days, not weeks.
Cy Hay, Product Manager |
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| DFTMAX Compression Backgrounder |
Scan design, the ubiquitous design-for-test technology, is based on a relatively simple concept: One or
more scan chains are constructed on a chip by serially tying together a set of internal registers and flip-flops.
Rohit Kapur & Robert Ruiz, Synopsys |
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