TetraMAX® ATPG automatically generates high quality manufacturing test patterns. It’s the only ATPG solution optimized for a wide range of test methodologies and integrated with Synopsys’ patented DFTMAX™ and DFTMAX Ultra, the leading test synthesis tools. The unparalleled ease-of- use and high performance provided by TetraMAX ATPG allows RTL designers to quickly create efficient, compressed test patterns for even the most complex designs.
- Key Benefits
- Improves product quality with comprehensive fault model support and power-aware test patterns
- Increases designer productivity by leveraging integration with Synopsys test compression tools
- Generates test patterns for even the largest and most complex SoCs
- Enables faster yield ramp by quickly isolating defect locations
- Extremely high capacity and performance
- Multicore support for accelerated run time
- Integrated graphical user interface, hierarchy browser and simulation waveform viewer
- Comprehensive scan and compression design rule checking
- Integrated fault simulator for grading structural test patterns
- Silicon diagnostics with automatic defect isolation
- TetraMAX DSMTest option enables advanced fault models and power-aware patterns
- TetraMAX IDDQ Test option available for quiescent test validation
- Integrated with Synopsys Yield Explorer for seamless volume diagnostics and yield analysis
Testing Complex ASICs
With TetraMAX ATPG, designers can generate high-quality manufacturing test patterns without compromising on high performance design techniques (Figure 1). While such techniques may impede other ATPG tools, TetraMAX ATPG is able to obtain coverage on the resulting complex logic.
TetraMAX ATPG supports internal three-state busses including implementations with pull-ups, pull-downs and charge storage. Similar to three-state busses, bidirectional I/O pads are also supported. To ensure ATE (automatic test equipment) requirements are met, TetraMAX ATPG provides a number of options to generate contention-free patterns for three-state logic.
Figure 1: Integrated test flow using TetraMAX ATPG
Memory Shadow Testing
Logic with fault effects which pass into a memory element, and logic that requires the outputs of the memory to set up a fault, are said to be “in the shadow” of the memory (Figure 2). Typically, the memory’s shadow affects a significant portion of the chip and causes a reduction in fault coverage. TetraMAX ATPG supports behavioral models of the memories to resolve the shadow effects and increase overall fault coverage for the circuit.
Figure 2: TetraMAX ATPG delivers high test coverage on a wide range of design styles
ATPG Design Rule Checking
TetraMAX ATPG’s design rule checker (DRC) identifies chip-level test issues. Violations can be analyzed by viewing them directly on the circuit using TetraMAX ATPG’s integrated graphical schematic viewer (Figure 3). Detailed violation information is available with context-sensitive help. TetraMAX ATPG’s fast DRC checks for the following problems:
- Flip-flops which violate scan chain design rules
- Asynchronous logic which may increase TetraMAX ATPG runtime or reduce fault coverage
- Clock generation logic and three- state busses that may be difficult to control during TetraMAX ATPG
- Test protocols which may cause incorrect behavior on the tester
TetraMAX ATPG’s DRC supports full scan and partial-scan test methodologies using mux-scan, clocked-scan, level sensitive scan design (LSSD) and proprietary schemes. For maximum flexibility, TetraMAX ATPG accepts user-defined constraints and initialization patterns required for proper scan chain shifting. Complete support is provided for designs with IEEE 1149.1/6 internal scan shifting protocols and related techniques that minimize the number of external I/O pins required for ATPG.
Figure 3: TetraMAX provides high-performance ATPG and advanced debug capabilities through its integrated graphical interface
High Defect-Coverage Testing
Many manufacturing defects will not be caught without additional high defect-coverage testing that specifically targets subtle nanometer defects.
With the TetraMAX DSMTest option, designers and test engineers can easily generate transition delay, path delay (Figure 4), bridging or dynamic bridging test patterns to further reduce defective parts per million (DPPM).
- Advanced features unique to the TetraMAX DSMTest option:
- PrimeTime® interface selects critical timing paths
- Full support for on-chip clocking such as PLLs
- Easy-to-use flow with graphical support for analysis and debug
- ATPG algorithms optimized for each specific delay testing mode
- Tester-ready patterns with complete timing
Figure 4: TetraMAX DSMTest automates testing of critical paths
TetraMAX DSMTest for Slack-based Transition Testing
TetraMAX DSMTest also enables ATPG to target subtle small delay defects inside ICs that could lead to failures when devices operate at full speed. Detecting these defects reduces DPPM compared to levels achieved by only using standard transition delay patterns and lowers the cost of production testing.
TetraMAX ATPG accesses precise timing information from PrimeTime, the industry's de factor sign-off static timing analysis engine, to achieve the timing resolution needed to accurately target small delay defects (Figure 5). No unnecessary yield loss occurs because there is no need to test the parts at faster-than-at-speed frequencies. Included with the TetraMAX DSMTest option, slack-based transition ATPG provides the following capabilities and benefits:
- Ultra-high-quality testing
- Highly-accurate timing information read from PrimeTime
- One-pass flow:
- Slack-based ATPG for small delay defects
- Standard transition delay ATPG for larger delay defects
- User control of targeted delay defect size
- Reports and histograms, including:
- Delay effectiveness metric
- Statistical delay quality level (SDQL) metric
- No design or DFT changes needed
Figure 5: TetraMAX small delay defect testing flow
Scan testing typically increases transistor switching activity by many times their peak functional-mode levels, leading to excessive power consumption. Too much power consumption during test can lead to unpredictable test results, including the failure of good devices on the tester, and unnecessary yield loss.
TetraMAX ATPG for power-aware test limits power consumption during test by automatically reducing switching activity to levels consistent with normal operation, based on designer-specified power budgets. This is achieved without compromising test coverage or the cost-savings advantage of DFTMAX and DFTMAX Ultra.
For many design teams, turn-around time for pattern generation is critical. TetraMAX ATPG takes advantage of the shared-memory architecture of widely available multicore computing machines to significantly cut the time needed to generate high-quality manufacturing tests. Optimizations in TetraMAX ATPG ensure that runtime performance scales well with the number of processor cores used, reducing runtimes when run on 2 to 32 cores while achieving the same high test coverage and low pattern count from operation on a uniprocessor machine. Multicore processing in TetraMAX ATPG is easily enabled with a single command line switch.
IDDQ testing is a method for enhancing the quality of IC tests by measuring the power supply current of a CMOS circuit. Defect free CMOS circuits draw very low levels of current during a quiescent state. IDDQ levels are typically an order of magnitude higher in the presence of a silicon defect. IDDQ testing targets physical defects that create a conduction path from the power supply to ground and result in excessive current draw.
TetraMAX ATPG generates a minimal set of high fault coverage patterns for IDDQ testing purposes, and constrains the test patterns to avoid excessive current during the quiescent state. The TetraMAX IDDQ Test option then accurately validates these patterns for low quiescence using Synopsys VCS® or other Verilog simulator, thereby ensuring the IDDQ patterns will work on the ATE.
In addition to identifying defective parts from manufacturing, TetraMAX ATPG can also isolate the location of defects on devices that fail TetraMAX ATPG test patterns. Automatic and accurate defect isolation is an important step to diagnose critical yield issues, both during production ramp as well as in volume manufacturing. TetraMAX ATPG diagnostics read the test patterns and tester failure data, which are the differences between measured and expected responses to those test patterns. They also report the fault candidate locations that most likely explain the faulty device behavior observed on the tester. TetraMAX ATPG diagnostics use advanced heuristics and a high-performance fault simulator for rapid and reliable results in a volume manufacturing environment.
Figure 6: Integrated flow between TetraMAX ATPG and Yield Explorer
Failure and Yield Analysis
TetraMAX ATPG is tightly integrated with Yield Explorer for further analysis of diagnostics results. To perform volume diagnostics, hundreds or thousands of failing parts are diagnosed with TetraMAX ATPG and Yield Explorer correlates those with specific failure mechanisms to determine the key design or systematic issues that are contributing to yield loss. Yield Explorer directly reads the accumulated diagnostics results from TetraMAX ATPG and loads them into a complete database of previous diagnostics results, other test data, multiple domains of design data, and if available, process data from the fab.
TetraMAX ATPG and Yield Explorer share standard interfaces for both fail data from the tester as well as physical design data. Physical data is important for both diagnostics and yield analysis. Diagnostics accuracy is significantly higher for defects caused by metal shorts and opens when the layout topology is incorporated into the diagnostics heuristics used by TetraMAX ATPG. For yield analysis physical data allows volume diagnostics results to be correlated with design-specific layout characteristics and determine which ones are the most sensitive to process variability.
- Data Formats, Simulation Testbenches and Tester Interfaces
TetraMAX ATPG supports popular industry standards for netlist and test pattern formats:
- Circuit netlist: Verilog, VHDL (87 and 93)
- Library: Verilog functional (Structural and UDPs)
- Timing exceptions: SDC
- Design layout: LEF/DEF
- Simulation testbench: Verilog (serial and parallel)
- Test Patterns: STIL, WGL, Verilog VCDE (input only)
- Tester fails: STDF (V4 and V4-2007)