Synopsys Synthesis-Based Test  

Accelerate Higher Quality, Lower Cost Test 
“We consider the Synopsys multicore ATPG capability essential to meeting our quality goals on time.”
Erich Van Stralen, ASIC Test Team Manager
Arrow Electronics

“Synopsys delivers test technology that keeps pace with our evolving requirements. As our designs become larger and more complex, test technology based on synthesis for defect coverage of digital logic will allow our designers to be more productive and continue to deliver high quality silicon on time.”
Bruce Fishbein, Director of Engineering
Cavium Networks

“From the beginning, we quickly got DFTMAX compression working on our designs thanks to its tight integration in the Synopsys Galaxy Implementation Platform.”
Seong-Heon Kim, CAD Manager & Director,
Dongbu Hitek

“Synopsys’ test solution helps us meet the challenging quality and cost requirements of our very complex designs.”
Scott Peterson, Division VP Engineering, Design Services
Exar Corporation

“Synopsys’ test solution has been the key to helping our COT customers achieve high test quality at low cost. In the future, we expect Synopsys to provide a total DFT solution for a chip using the newly obtained memory IP and BIST technology.”
Michiaki Emori, Deputy General Manager
SoC Design Engineering Div, Common IP & Technology Development and Manufacturing Unit

Fujitsu Semiconductor Limited

“Design Compiler has made fast implementation time a reality by encapsulating synthesis and design-for-test into a single comprehensive solution that addresses our most challenging design and test requirements.”
Albert Li, Director, Design Service Division
Global Unichip Corp.

“Using DFTMAX compression to reduce test data volume for our new HDTV chip allowed us to apply all the test patterns at one time and take full advantage of the higher test quality possible with DSM tests.”
Woo-Hyun Paik , Research Fellow, System IC Business Unit
LG Electronics

“From design to production, DFTMAX compression and TetraMAX ATPG are key components for our multi-clock, single pass, deep-submicron, device DFT architecture and test generation.”
Chris Ryan Ph.D., Principal Member Technical Staff, EDA, DFT
Maxim Integrated Products

“Synopsys’ test solution helps us maintain high defect coverage while meeting our demanding tapeout schedules.”
Alvin Ling , Director of CAD Support & License Management, Technology Infrastructure Group
National Semiconductor

“We selected Yield Explorer because this solution has all the traditional yield analysis features combined with unique design-centric, volume diagnostics capabilities. Yield Explorer was able to handle gigabytes of data per day from the test floor and combine it with the design and fab data.”
Bruce Cory, Manager DFx Technology
NVIDIA

“Our product teams can ramp-up to volume testing faster with Synopsys power-aware test because we spend less time debugging power-related issues. An added benefit is that we can test our products across a much wider range of operating environments, including lower supply voltage conditions.”
Jessy Chen, Vice President and Spokesman
Realtek Semiconductor Corporation

“We utilize DFTMAX and TetraMAX successfully in our flow to meet our demanding design-for-test requirements.”
Toshiharu Asaka, Senior Manager, Design for Test Technology Development Department
Renesas Electronics Corporation

“Manufacturing highly reliable products at low cost is essential to our business model. Having design-for-test built into Design Compiler makes it easy to implement cost-effective test that simultaneously meets timing, area and power targets.”
Hungbok Choi, Principal Engineer, Design Technology Team, System LSI Division
Samsung

“Synopsys’ continual innovation in areas such as slack-based at-speed test and power-aware test has helped our member companies consistently meet their strict quality requirements.”
Takashi Aikyo, Senior Manager, Test & Diagnosis Group, Development Department-2
Semiconductor Technology Academic Research Center

“DFTMAX compression for pin-limited test reduced test time and data by more than 95 percent while maintaining high defect coverage, helping us exceed the aggressive cost and quality goals for our product.”
Narasimha Nookala, Senior Director IC Engineering
Silicon Image

“Our ongoing collaboration with Synopsys has produced several widely adopted, leading-edge test technologies such as managing power of the device on the tester and high defect coverage using a limited number of pins. We continue to work together on more technology embedded in synthesis to further increase our test quality, control test costs and allow us to quickly analyze defective silicon under very tight schedules.”
Roberto Mattiuzzo, Design for Excellence Manager in Technology R&D - Central CAD and Design Solutions
STMicroelectronics

“Synopsys has a long history of introducing key test technologies to help our designers and customers achieve higher test quality and a lower cost of test. DFTMAX and TetraMAX are an important part of the TSMC Reference Flow.”
Tom Quan, Deputy Director, Design Methodology & Service Marketing, Design Technology Platform
TSMC

“DFTMAX compression and TetraMAX® ATPG have repeatedly allowed us to achieve these goals for our latest mixed-signal designs. The new enhancements in DFTMAX compression for pin-limited test give us the full benefits of compression on our lowest pin-count mixed-signal designs.”
Jean-Louis Cols, Vice President of Product Development
Wolfson Microelectronics



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