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| Jun 11, 2013 | Synopsys Unveils New Synthesis-Based Test Technology Delivering Up to 3X Higher Compression
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| | Sep 20, 2011 | Synopsys Enhances Volume Diagnostics Solution to Accelerate Yield Ramp
Innovations in TetraMAX ATPG and Yield Explorer Increase Throughput and Ease Deployment
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| | Sep 20, 2011 | Synopsys' DesignWare STAR Memory System Shipped in 1 Billion Chips
Design Teams Worldwide Quickly Achieve Test and Repair Quality Goals for Embedded Memories
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| | Nov 01, 2010 | Synthesis-Based Test Technology Increases Designer Productivity
Synopsys’ new test technology enables designers to achieve optimal quality-of-results and eliminate time-consuming iterations between design and test.
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| | Oct 26, 2010 | Power-Aware Test Speeds Time to Volume Production at Realtek
Reducing Power Consumption and IR Drop During Manufacturing Test Enables Faster Delivery of Working Silicon
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| | Sep 08, 2010 | Synopsys DFTMAX Compression Cuts Pin-Limited Test Cost by 95 Percent at Silicon Image
Using the new pin-limited test capability in Synopsys’ DFTMAX, Silicon Image designers easily implemented test compression for the mixed-signal chip in just two days, substantially reducing test time, data and cost while achieving high test coverage.
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| | Nov 03, 2009 | Synopsys TetraMAX ATPG Cuts Test Development Schedule at Arrow Electronics
Multicore Processing Speeds Runtime by 3X, Accelerates Time-to-Quality
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| | Nov 02, 2009 | Synopsys Extends DFTMAX Compression to Reduce the Cost of Pin-Limited Test
Delivers predictable high compression with only one pair of test data pins
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| | Oct 28, 2009 | NVIDIA Adopts Synopsys Yield Explorer to Reduce Time to Volume
Design-centric yield management enables product engineers to achieve rapid yield ramp and provide cost-effective yield control in volume production
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