Join us for this special lunch event at SNUG Silicon Valley and hear your peers discuss how they are utilizing new Synopsys synthesis technologies to meet the challenges of today's complex designs at both established and emerging nodes. Panelists will discuss how they are using Design Compiler Graphical to achieve smaller area, reduced congestion and faster convergence. Additionally, you will hear how the latest capabilities in DC Explorer's RTL analysis can help you develop high-quality RTL more quickly.
Santi Adamo, Design Manager, STMicroelectronics
Tatsuya Nakae, Director of SoC Design Methodology, Fujitsu Semiconductor
Hatem Yazbek, Technical Director, Broadcom
RTL design, CAD and physical design engineers/managers
|Following the technical presentations, two|
raffles will be held for Pebble Smartwatches.
March 25, 2014
12:00 p.m. to 1:30 p.m.
SNUG Silicon Valley
Santa Clara Conventions Center
5001 Great America Parkway
Santa Clara, CA 95054
Add the Design Compiler Lunch and Learn to your
SNUG Silicon Valley agenda to Register Now!