Conventional scan testing routinely increases power consumption in devices to levels far exceeding mission-mode power levels. This can lead to unnecessary yield loss on the production line that requires substantial time and effort to diagnose. Today’s nanometer designs are particularly susceptible to these issues, not only due to their high flop counts, but also the need to employ at-speed testing to cover subtle manufacturing defects.
Automation that addresses power problems during test not only should have minimal impact on power consumption during normal operation, but also should work transparently with the latest multi-voltage design methodologies.
Now, designers can avoid test power problems from the outset with new power-aware test technology in the Galaxy™ Implementation Platform.
TetraMAX® ATPG produces test patterns with a low-power footprint without compromising test coverage or the cost-savings advantage of DFTMAX compression. Power-aware test provides advanced automation to:
- Perform low-power fill and scan gating as needed to reduce power during scan shifting
- Generate patterns based on a designer-specified power budget to reduce power during capture mode
- Gate off DFT logic in functional mode to reduce power during normal operation
- Simplify the implementation of DFT in designs with multiple voltage domains
Synopsys’ silicon-proven power-aware test solution makes it possible to maintain high test quality without incurring unnecessary yield loss, thereby lowering the cost of production testing.
Power-Aware Test: Increasing Yield
Conventional compression tools create patterns that force the device under test to consume up to ten times more power compared to normal operation, leading to IR drop and overheating. Dr. T.W. Williams introduces capabilities in DFT MAX compression and TetraMAX ATPG that manages device power consumption at the tester, resulting in higher yield.
Tom Williams, Synopsys Fellow
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