| Feb 28, 2012 | BiTMICRO Selects Synopsys for Chip Design Automation
Two third-generation SSD controllers taped out using Synopsys' Galaxy Implementation and Discovery Verification Platforms
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| Feb 09, 2012 | CSR Selects Synopsys for Advanced-Node SoC Design
Adoption of Synopsys Galaxy Platform Driven by Superior Results for ARM CPU-based SoCs
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| Dec 14, 2011 | GUC Achieves Gigahertz+ Frequency on ARM Processor with Synopsys IC Compiler
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| Dec 14, 2011 | Synopsys Enables Silicon Success for GLOBALFOUNDRIES First Complex 20-nm Design
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| Dec 05, 2011 | Industry Leaders Achieve Significant Power and Performance Gains With Synopsys' Low Power Solution
Industry Leaders Achieve Significant Power and Performance Gains With Synopsys' Low Power Solution
Advanced Solution Now in Mainstream Usage with More Than 125 Successful Tapeouts
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| Oct 18, 2011 | Synopsys Low Power Solution Accelerates Time to Market for 3G Mobile IC
CYIT Completes Tapeout Five Weeks Ahead of Schedule with First-Pass Silicon Success
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| Apr 19, 2011 | Synopsys Design Compiler Graphical Cuts Design Time at Exar
Exar Engineers Detected and Fixed Routing Congestion Hot Spots in Synthesis Before Hand-off to Physical Implementation
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| Mar 28, 2011 | Synopsys Unveils DC Explorer for Early RTL Exploration
Solution Accelerates Design Implementation through Early Exploration While Tolerating Incomplete Data
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| Jan 31, 2011 | Synopsys Galaxy Implementation Platform Addresses Gigascale Design
Latest Release Includes Scalability, Convergence and Throughput for Large IC Implementation on Advanced Node Technology
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| Jan 10, 2011 | Synopsys Speeds Equivalence Checking by 2X at Nuvoton
Productivity Advantage Over Existing Solution Cited as Main Driver to Standardization on Formality
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| Nov 10, 2010 | Synthesis-Based Test Technology Increases Designer Productivity
Synopsys’ new test technology enables designers to achieve optimal quality-of-results and eliminate time-consuming iterations between design and test.
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| Oct 26, 2010 | Power-Aware Test Speeds Time to Volume Production at Realtek
Reducing Power Consumption and IR Drop During Manufacturing Test Enables Faster Delivery of Working Silicon
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| Sep 08, 2010 | Synopsys DFTMAX Compression Cuts Pin-Limited Test Cost by 95 Percent at Silicon Image
Using the new pin-limited test capability in Synopsys’ DFTMAX, Silicon Image designers easily implemented test compression for the mixed-signal chip in just two days, substantially reducing test time, data and cost while achieving high test coverage.
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| Aug 09, 2010 | Synopsys Galaxy Implementation Platform Used by TSMC for 28nm Process
Product Qualification Vehicle Test Chip Tapeout Includes Advanced Routing Rules, Low Power and Signoff Capabilities
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| Jul 27, 2010 | Synopsys' Design Compiler Graphical Shortens Design Schedule at Oticon
Synopsys announced that Oticon taped out the digital signal processor (DSP) chipset for their next-generation hearing-aid devices ahead of schedule using Synopsys' Design Compiler™ Graphical RTL Synthesis, a key component of the Galaxy™ Implementation Platform.
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| Jun 10, 2010 | Samsung Achieves First-Pass 32nm Silicon Success Using Synopsys Galaxy Implementation Platform
Synopsys announced that Samsung Electronics' Foundry business (Samsung Foundry) has successfully taped out its first 32-nanometer (nm) system-on-chip (SoC) design using Synopsys' Galaxy™ Implementation Platform.
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| Mar 29, 2010 | Design Compiler 2010 Doubles Productivity of Synthesis and Place and Route
Delivers Five Percent Correlation to Layout, Floorplan Exploration and 2X Faster Runtime with Multicore Technology
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| Feb 09, 2010 | Yamaha Tapes Out Their Latest Graphics LSI Chip with Synopsys Design Compiler Graphical
Eliminates Iterations Between Synthesis and Place and Route to Predictably Meet Performance and Time-to-Market Goals
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| Nov 03, 2009 | Synopsys TetraMAX ATPG Cuts Test Development Schedule at Arrow Electronics
Multicore Processing Speeds Runtime by 3X, Accelerates Time-to-Quality
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| Nov 02, 2009 | Synopsys Extends DFTMAX Compression to Reduce the Cost of Pin-Limited Test
Delivers predictable high compression with only one pair of test data pins
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| Oct 28, 2009 | NVIDIA Adopts Synopsys Yield Explorer to Reduce Time to Volume
Design-centric yield management enables product engineers to achieve rapid yield ramp and provide cost-effective yield control in volume production
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| Jun 03, 2009 | Synopsys’ Eclypse Low Power Solution Enables Fujitsu Microelectronics to Cut Design Cycle by 30 Percent
IEEE 1801 Enabled Implementation Flow Qualified for 65- and 40-nm Designs
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| Oct 28, 2008 | Synopsys DFT MAX Compression Achieves Mainstream Usage at 90 Nanometers and Below
Unique Power-Aware Test Capabilities Reduce Yield Loss
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| Mar 31, 2008 | Synopsys Extends Design Compiler to Predict and Alleviate Routing Congestion
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, today unveiled its new Design Compiler® Graphical synthesis product that shortens implementation time for system-on-chip (SoC) devices by helping RTL designers avoid wire-routing congestion problems that typically occur during detailed route.
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