Test ITC 2010 


Come see Synopsys at this year’s International Test Conference 2010 at the Austin Convention Center, Austin, TX,
October 31 – November 5.

Join us for the 18th Annual Synopsys Test Special Interest Group (SIG) Event
Monday, November 1
6:45 p.m. - 9:30 p.m
Austin Hilton Hotel
Register Now!

Appetizers and cocktails will be served, followed by a sit-down dinner. Test experts from leading companies will present how they are deploying Synopsys’ synthesis-based test and yield analysis solution to address their most challenging requirements, including test and repair of embedded memories, test of designs with complex clocking schemes, power-aware test and volume diagnostics for rapid yield learning.

Robert Aitken of ARM will host the following guest speakers at the 2010 Test SIG event:
  • Amitava Majumdar, AMD
  • Chris Ryan, Maxim Integrated Products
  • Kun Young Chung, Samsung Electronics
  • Florent Garait, ST-Ericsson

Visit us at Booth #206
We’ll demonstrate how Synopsys’ DFTMAX™ compression, TetraMAX® ATPG, DesignWare® STAR™ Memory System and Yield Explorer can help you increase productivity, accelerate time-to-quality and lower test cost. To learn more about Synopsys’ test solution, please visit Synopsys RTL Synthesis & Test.

Synopsys at the Technical Sessions
  • Test Clinic: “Logic and Memory Testing for SOCs” Monday, Nov. 1, 8:30 a.m. – 4:30 p.m.
  • Tutorial 6: “Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices” Monday, Nov. 1, 8:30 a.m. – 4:30 p.m.
  • Tutorial 7: “Testing TSV-based 3-D Stacked ICs” Monday, Nov. 1, 8:30 a.m. – 4:30 p.m.
  • Session 9.1: “Increasing PRPG-based Compression by Delayed Justification” Wednesday, Nov. 3, 8:30 a.m. – 10:00 a.m.
  • Session 12.2: “Highly Efficient Parallel ATPG Based on Shared Memory” Wednesday, Nov. 3, 10:30 a.m. – 12:00 p.m.
  • Session 21.2: “RT-level Design-for-Testability and Expansion of Functional Test Sequences for Enhanced Defect Coverage” Thursday, Nov. 4, 8:30 a.m. – 10:00 a.m.
  • Lecture 2: “PhD Dissertation Award Forum: Final Round” Tuesday, Nov. 2, 4:00 p.m. – 5:30 p.m.
  • Workshop 1: “3D-TEST – 1st IEEE International Workshop on Testing Three-Dimensional Stacked ICs” Thursday, Nov. 4, 4:00 p.m. – Friday, Nov. 5, 4:00 p.m.
  • Workshop 2: “TVHSAC – 2nd IEEE International Workshop on Test and Validation of High-Speed Analog Circuits” Thursday, Nov. 4, 4:00 p.m. – Friday, Nov. 5, 4:00 p.m.

We look forward to seeing you at ITC 2010!

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