Design Compiler Graphical 

Design Compiler Graphical, the new member in the Design Compiler® family, helps RTL designers avoid wire-routing congestion problems before they occur. The tool utilizes topographical technology in common with IC Compiler to accurately model the demand and capacity of global routing. It’s the industry’s only synthesis solution that:
  • Predicts congestion "hot spots" early in the design flow
  • Provides visualization and analysis of the congested circuit regions
  • Performs synthesis optimizations to minimize congestion in these areas.

Congestion can make a design extremely difficult to route without adversely affecting the physical constraints and timing margins. Correcting these problems often leads to multiple, lengthy iterations between logical and physical implementation that can add weeks to your project schedule.

Using Design Compiler Graphical, you can predict, visualize and alleviate routing problems during synthesis to create a better starting point for physical implementation and significantly lower project time, effort and cost.

Perspective: Boost your design productivity
Design Compiler Graphical, the newest member of the Design Compiler product family, creates a better starting point for physical implementation and can shave weeks off your design schedule. Hear what Antun Domic, senior vice president and general manager of Synopsys' Implementation Group, has to say about this new breakthrough in design automation.

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