Overview
BSD Compiler is an automated tool for the synthesis and verification of boundary scan logic in ASICs and ICs within the Design Compiler® synthesis environment. BSD Compiler synthesizes boundary scan from the user’s RTL description utilizing DesignWare® JTAG components. After synthesis, a powerful and unique compliance checker in BSD Compiler verifies the boundary scan logic for compliance to the IEEE 1149.1/.6 standard. BSD Compiler automatically creates a boundary scan description language (BSDL) file for board-level test and generates functional and DC parametric patterns for manufacturing test.

Download Datasheet

Key Benefits

• Easy implementation of boundary scan in the familiar Synopsys synthesis environment
• Eliminates late stage iterations by early prediction of boundary scan impact on timing
• Quickly verifies conformance to the IEEE 1149.1 standard

Figure 1: Boundary Scan Flow

BSD Compiler Features

Includes pre-verified boundary scan DesignWare components

Timing and area driven boundary scan implementation using new boundary scan optimization algorithm

Powerful IEEE 1149.1 compliance checking

Easy-to-use interface to debug 1149.1 compliance errors

Automatic BSDL file generation

Automatic functional and DC parametric pattern generation

Verifies compliance and generates a BSDL file and manufacturing patterns on designs with existing boundary scan logic

Figure 2: BSD Compiler provides a highly integrated flow for boundary scan synthesis, verification and pattern generation in the Design Compiler environment

Boundary Scan Synthesis and Optimization
BSD Compiler is tightly integrated in the Design Compiler synthesis flow, which ensures optimized implementation of design with boundary scan logic. After reading the RTL description, BSD Compiler synthesizes boundary scan logic based on the user’s JTAG specification. Once the design is mapped to a technology library, BSD Compiler optimizes the boundary scan architecture by intelligently selecting boundary scan cells to meet top-level area and timing constraints.

BSD Compiler synthesizes boundary scan logic using Synopsys DesignWare JTAG components which are included with the tool. Since the tool uses optimized DesignWare boundary scan components, the need to manually design the boundary scan cells is eliminated. The DesignWare test access port (TAP) is configurable to accommodate individual designs, and with a few simple commands in BSD Compiler, IEEE 1149.1 compliance is assured early in the design cycle.

Powerful IEEE 1149.1 Compliance Checking
One of the unique features of BSD Compiler is its ability to perform 1149.1 compliance checking utilizing symbolic simulation techniques. This eliminates the need for extensive gate-level simulation to verify conformance to the IEEE 1149.1 standard. BSD Compiler provides an easy-to-use interface to debug problems due to 1149.1 compliance errors.

The compliance checking capability also supports designs with existing boundary scan logic.

BSD Compiler provides a highly integrated flow for boundary scan synthesis, verification and pattern generation in the Design Compiler environment.

Verification
BSD Compiler automatically generates a BSDL file, the standard description language for devices complying with the IEEE 1149.1/.6 standard. BSD Compiler generates both functional and DC parametric patterns for manufacturing test. BSD Compiler can also generate a BSDL file and test patterns for designs with existing boundary scan logic.

Netlist, Test Vector Interface
BSD Compiler supports popular industry standards for RTL input and test pattern formats:

• RTL Input: Verilog, VHDL
• Test Bench: Verilog, VHDL-87
• Test Patterns: WGL, STIL