Continuing the trend of delivering innovative synthesis technology, Synopsys offers Design Compiler 2010 that provides a twofold speedup of the synthesis and physical implementation flow. As geometries shrink to 65nm and smaller process technologies, design complexities increase multifold making it extremely difficult for designers to complete designs on schedule. The nanometer effects such as coupling capacitances between parallel interconnects have much higher impact on interconnect delays and need to be considered during synthesis for predictable design implementation. Moreover, floorplan issues, such as routing congestion due to macro placement, need to be fixed early in the design cycle to avoid iterations. Designers need an RTL synthesis solution that improves schedule predictability by producing a better starting point to physical implementation and avoids costly iterations between synthesis and place-and-route.
- Download Datasheet
Design Compiler 2010 extends topographical technology to produce physical guidance to IC Compiler, place-and-route solution, tightening timing and area correlation to 5% while speeding-up IC Compiler placement by 1.5X. It applies additional physical optimization techniques and considers the effects of smaller geometries such as coupling capacitances for accurate delay modeling. The physical guidance passed to IC Compiler streamlines the flow for a faster, predictable design implementation. Design Compiler 2010 also provides RTL designers access to IC Compiler’s design planning capabilities from within the synthesis environment. With the push of a button, RTL designers can perform what-if floorplan exploration to identify and fix floorplan issues early and achieve an optimal floorplan efficiently. Additionally, Design Compiler 2010 includes a new, scalable infrastructure designed to deliver significant runtime speedup on multicore compute servers. It employs an optimized scheme of distributed and multithreaded parallelization techniques, delivering 2X faster runtime on quad-core compute servers while ensuring zero deviation of the synthesis results. With these new technology advances, Design Compiler 2010 helps designers reduce iterations and cut synthesis and placement runtime significantly.
Figure 1: Design Compiler 2010
Figure 2: Timing correlation
Figure 3: Area correlation
- Key Benefits
- Better starting point for physical implementation
- 5% Correlation to layout
- 1.5X faster placement runtime
- Push-button floorplan exploration
- 2X faster runtime on quad-core compute servers
Physical Guidance to IC Compiler
With designs becoming more complex along with shrinking geometries, designers require even tighter correlation between synthesis and layout results. Additionally, as geometries become smaller, the coupling capacitance between adjacent parallel wires is much higher due to the fact that spacing between wires is smaller and the relative heights of the wires are greater. Hence the impact of coupling capacitance is much higher on design delays and needs to be accounted for in synthesis.
Topographical technology in Design Compiler 2010 is extended to create physical guidance for IC compiler bringing synthesis timing and area results within 5% of layout while speeding up IC Compiler placement step by 1.5X. It performs additional physical optimizations during synthesis to create a better starting for physical implementation and accurately models the effects of smaller geometries such as coupling capacitance. It further seeds IC Compiler placement via physical guidance to streamline the implementation flow and accelerate placement runtimes.
Figures 2 and 3 illustrate improvements in timing and area correlation, respectively, across multiple designs using physical guidance. On the X-axis are the designs and the Y-axis is % delta between synthesis and layout results. The light purple bars (on the left) show the delta between synthesis and layout without passing physical guidance. The purple bars show the delta for the same designs with physical guidance technology. As shown in these figures, results are consistently within 5% when physical guidance is passed from Design Compiler 2010 to IC Compiler. Figure 4 shows placement runtime improvements using physical guidance technology. On the X-axis are the designs and on the Y-axis are the runtimes in hours. The light purple bars represent IC Compiler placement runtime without physical guidance and the purple bars represent IC Compiler placement runtime with physical guidance. As illustrated by the figure IC Compiler placement runtime is much faster when physical guidance is passed from Design Compiler 2010, averaging 1.5X faster.
Figure 4: IC Compiler placement runtime
Push-Button Floorplan Exploration for Faster Design Convergence
Until now, if changes to design floorplans were needed, RTL designers had to ask their counterparts on physical design teams to adjust the floorplan, resulting in iterations between the teams. With immense time-tomarket pressures, designers need a solution to reduce these iterations. Design Compiler 2010 provides RTL designers access to IC Compiler design planning capabilities from within the familiar synthesis environment. After detecting design issues, such as routing congestion or timing violations due to floorplan characteristics, RTL designers can now amend the floorplan and resynthesize the design with an updated floorplan without ever leaving the synthesis environment. The IC Compiler design planning menus have been simplified to give RTL designers ease of use for simple floorplan modifications. An option is available for expert users to utilize the full, advanced floorplanning capabilities. The Design Compiler 2010 and IC Compiler design planning link is transparent to users hence no setup or data transfer is required. Once the designer has created an optimal floorplan, they can save it to be used for physical implementation downstream.
Figure 5 shows an example of design layout where congestion hot spots occurred due to a very narrow channel between macros as shown in Design Compiler Graphical’s layout viewer. A click on the “Start Design Planning” menu option in Design Compiler (see Figure 6) opens a new IC Compiler design planning window with the design floorplan loaded for editing. With very few maneuvers RTL designers can move the macro to eliminate this narrow channel as shown in figure 7. Once the floorplan edits are made, designers can save the floorplan as shown in figure 8 and re-synthesize the design with the updated floorplan. As shown by the congestion map in figure 9, with the updated floorplan, routing congestion has been eliminated and the design is ready for physical implementation.
Design Compiler 2010 helps RTL designers perform a what-if analysis of floorplan quickly and efficiently so that they can be ensured that the design will meet its targets during physical implementation without requiring iterations.
Figure 5: Routing congestion identified in Design Compiler
Figure 6: Accessing IC Compiler design planning within synthesis
Figure 7: Floorplan editing to address routing congestion
Figure 8: Saving Floorplan updates
Figure 9: Congestion eliminated
New Infrastructure for Multicore
The advent of multicore processors in compute platforms has boosted the processing power available to designers. Design Compiler 2010 introduces a new scalable infrastructure to take advantage of multicore compute servers. Using an optimized scheme of distributed and multithreaded parallelization, Design Compiler 2010 delivers a 2X improvement in runtimes on quad core platforms. The new infrastructure delivers runtime benefits without deviating the quality of results. Figure 10 compares Design compiler 2010 runtimes across multiple designs on single core vs. quad core machines. On the X-axis are designs and on the Y-axis are the runtimes in hours. The light purple bars represent Design Compiler 2010 runtimes using a single core machine and the purple bars represent runtimes using quad core machines for the same design.As seen in the figure, Design Compiler 2010 is, on average, 2X faster on quad core compute servers.
Figure 10: Synthesis runtime
The new technology advances in Design Compiler 2010 double the productivity of synthesis and place and route by enabling RTL designers to achieve an optimal floorplan efficiently, delivering 5% correlation to layout and 1.5X faster placement runtimes, and 2X faster synthesis on quad core platforms.
Technologies of Design Compiler 2010 are available today. The physical guidance to IC Compiler and floorplan exploration are available in Design Compiler Graphical. The new infrastructure for multicore compute servers is available in DC ultra and Design Compiler Graphical.